I/O DEVICE AND COMPUTING HOST INTEROPERATION

• US 20130297894A1
• Filed: 07/05/2013
• Published: 11/07/2013
• Est. Priority Date: 08/09/2011
• Status: Abandoned Application

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: COHEN, Earl T., CANEPA, Timothy Lawrence
• Application Number:
  US13/936,010
• Publication Number:
  US 20130297894A1
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

An I/O device is coupled to a computing host. In some embodiments, the device is enabled to utilize memory of the computing host not directly coupled to the device to store information such as a shadow copy of a map of the device and/or state of the device. Storage of the shadow copy of the map enables one or both of the device and the computing host to utilize the shadow copy of the map, such as to decrease read latency. Storage of the state enables the device to save volatile state that would otherwise be lost when the device enters a low-power state. In some embodiments, the device implements one or more non-standard modifiers of standard commands. The non-standard modifiers modify the execution of the standard commands, providing features not present in a host protocol having only the standard commands.

Claims

1-32. -32. (canceled)

33. A method comprising:

receiving, via an external interface of an I/O device, write commands from a computing host;

writing data of the write commands to respective locations in a Non-Volatile Memory (NVM) of the I/O device;

maintaining, by the I/O device, a map comprising associations between Logical Block Addresses (LBAs) of the write commands and the respective locations in the NVM; and

storing, by the I/O device, at least a portion of the map in a memory of the computing host.

34. The method of claim 33, further comprising:

determining whether the stored portion has information corresponding to LBAs associated with at least one read command received via the external interface of the I/O device.

35. The method of claim 34, further comprising:

retrieving the information, selectively as available, subsequent to and in view of the determining.

36. The method of claim 33, further comprising:

determining whether the stored portion comprises information corresponding to LBAs associated with at least a first write command of the write commands; and

changing the stored portion, via further storing by the I/O device, selectively as required in view of the determining, such that the stored portion comprises the information corresponding to LBAs associated with the first write command.

37. The method of claim 33, wherein the stored portion is a cache of at least a portion of the map.

38. The method of claim 33, wherein the stored portion is a shadow copy of at least a portion of the map.

39. The method of claim 33, wherein the memory of the computing host comprises a main memory of the computing host.

40. The method of claim 33, wherein the memory of the computing host comprises an I/O space memory of the computing host.

41. The method of claim 33, wherein at least a portion of the memory of the computing host is in an address space accessible by the I/O device.

42. The method of claim 33, wherein the map is non-volatilely stored in the NVM.

43. The method of claim 33, wherein the memory of the computing host comprises a volatile memory.

44. A system comprising:

means for receiving, via an external interface of an I/O device, write commands from a computing host;

means for writing data of the write commands to respective locations in a Non-Volatile Memory (NVM) of the I/O device;

means for maintaining, by the I/O device, a map comprising associations between Logical Block Addresses (LBAs) of the write commands and the respective locations in the NVM; and

means for storing, by the I/O device, at least a portion of the map in a memory of the computing host.

45. The system of claim 44, further comprising:

means for determining whether the stored portion has information corresponding to LBAs associated with at least one read command received via the external interface of the I/O device.

46. The system of claim 45, further comprising:

means for retrieving the information, selectively as available, subsequent to and in view of the determining.

47. The system of claim 44, further comprising:

means for determining whether the stored portion comprises information corresponding to LBAs associated with at least a first write command of the write commands; and

means for changing the stored portion, via further storing by the I/O device, selectively as required in view of the determining, such that the stored portion comprises the information corresponding to LBAs associated with the first write command.

48. The system of claim 44, wherein the stored portion is a cache of at least a portion of the map.

49. The system of claim 44, wherein the stored portion is a shadow copy of at least a portion of the map.

50. The system of claim 44, wherein the memory of the computing host comprises a main memory of the computing host.

51. The system of claim 44, wherein the memory of the computing host comprises an I/O space memory of the computing host.

52. The system of claim 44, wherein at least a portion of the memory of the computing host is in an address space accessible by the I/O device.

53. The system of claim 44, wherein the map is non-volatilely stored in the NVM.

54. The system of claim 44, wherein the memory of the computing host comprises a volatile memory.