CHECKPOINTED BUFFER FOR RE-ENTRY FROM RUNAHEAD

• US 20130297911A1
• Filed: 05/03/2012
• Published: 11/07/2013
• Est. Priority Date: 05/03/2012
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Rozas, Guillermo J., Serris, Paul, Vanderschoot, Hens, Segelken, Ross, Boggs, Darrell, Hoyt, Brad, Ramakrishnan, Sridharan, Ekman, Magnus
• Granted Patent: US 9,875,105 B2
• Time in Patent Office: Days
• US Class Current: 712/205
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3814 Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
• CPC Class Codes: G06F 9/3863 using multiple copies of the architectural state, e.g. shadow registers

Abstract

Embodiments related to re-dispatching an instruction selected for re-execution from a buffer upon a microprocessor re-entering a particular execution location after runahead are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic, one or more execution mechanisms for executing a retrieved instruction provided by the fetch logic, and scheduler logic for scheduling the retrieved instruction for execution. The example scheduler logic includes a buffer for storing the retrieved instruction and one or more additional instructions, the scheduler logic being configured, upon the microprocessor re-entering at a particular execution location after runahead, to re-dispatch, from the buffer, an instruction that has been previously dispatched to one of the execution mechanisms.

Claims

1. A microprocessor, comprising:

fetch logic;

one or more execution mechanisms for executing a retrieved instruction provided by the fetch logic; and

scheduler logic for scheduling the retrieved instruction for execution, the scheduler logic including a buffer for storing the retrieved instruction and one or more additional instructions, the scheduler logic being configured, upon the microprocessor re-entering at a particular execution location after runahead, to re-dispatch, from the buffer, an instruction that has been previously dispatched to one of the execution mechanisms.

2. The microprocessor of claim 1, the buffer being stored in a single array comprising 2N entries arranged in pairs.

3. The microprocessor of claim 2, the scheduler logic including an address bit configured to identify whether a selected address for a selected entry in storage cells corresponds to a checkpointed version of the buffer or a non-checkpointed version of the buffer.

4. The microprocessor of claim 1, the buffer comprising:

a read pointer for reading a selected instruction held in the buffer in preparation for dispatching the selected instruction for execution; and

a de-allocation pointer for causing the selected instruction to be logically removed from the buffer after the selected instruction completes.

5. The microprocessor of claim 4, the buffer further comprising:

a replay pointer for causing a selected instruction to be re-dispatched for re-execution during replay; and

a restart instruction pointer for tracking an address following a last complete instruction held in the buffer, the restart instruction pointer directing an instruction pointer for the fetch logic so that the fetch logic fetches another instruction from outside of the buffer while the selected instruction is re-dispatched for re-execution.

6. The microprocessor of claim 5, the scheduler logic further comprising:

a checkpointed version of the buffer comprising an instruction causing entry into runahead and a plurality of subsequent instructions; and

a non-checkpointed version of the buffer operating in a working state during runahead;

where, after runahead, the scheduler logic is configured to reset the buffer to the checkpointed version.

7. The microprocessor of claim 6, the buffer being configured to store a plurality of bundles of micro-operations, each micro-operation corresponding to one or more instruction set architecture (ISA) instructions or parts of ISA instructions, the scheduler logic further comprising a boundary instruction pointer for tracking a boundary between a last bundle for a complete ISA instruction held in the buffer and a subsequent bundle belonging to an incomplete ISA instruction held in the buffer, where the restart instruction pointer is configured to track an address following a last complete instruction held in the buffer as tracked by the boundary instruction pointer.

8. The microprocessor of claim 6, where the checkpointed version is generated by the scheduler logic upon entry into runahead.

9. The microprocessor of claim 8, where the checkpointed version includes one or more vacancies.

10. The microprocessor of claim 1, the fetch logic and the scheduler logic being upstream of a pipeline included in the microprocessor.

11. The microprocessor of claim 1, the scheduler logic being included in the fetch logic and/or decode logic for decoding an instruction for execution at one of the execution mechanisms of the microprocessor.

12. A method for re-dispatching an instruction to be re-executed at a microprocessor, the method comprising:

reading an instruction selected for re-execution upon the microprocessor re-entering a particular execution location after runahead, the instruction held in a buffer for re-dispatch to one or more execution mechanisms of the microprocessor;

after reading the selected instruction, re-dispatching the instruction; and

from outside of the buffer, fetching another instruction while the selected instruction is re-executed.

13. The method of claim 12, further comprising, in response to entry into runahead, generating a checkpointed version of the buffer, the checkpointed version comprising an instruction causing entry into runahead and a plurality of subsequent instructions.

14. The method of claim 13, further comprising, after runahead and before reading the instruction held in the buffer, resetting a non-checkpointed version of the buffer to the checkpointed version.

15. The method of claim 14, where setting the non-checkpointed version of the buffer to the checkpointed version includes:

copying a checkpointed version of a de-allocation pointer to a read pointer, the de-allocation pointer configured to cause the instruction to be logically removed from the buffer after the selected instruction completes, the read pointer configured to read the instruction in preparation for execution; and

copying the checkpointed version of the de-allocation pointer to a replay pointer, the replay pointer configure to cause a selected instruction to be re-dispatched for re-execution during replay.

16. The method of claim 15, where re-dispatching the instruction comprises:

reading the instruction as indicated by the read pointer;

dispatching the instruction to the one or more execution mechanisms; and

logically removing the instruction from the buffer upon completion as indicated by the de-allocation pointer.

17. The method of claim 16, where re-dispatching the instruction further comprises replaying the instruction as indicated by the replay pointer responsive to an execution stall.

18. The method of claim 16, where fetching another instruction from outside the buffer comprises copying a restart instruction pointer to an instruction pointer for fetch logic of the microprocessor so that the fetch logic fetches the other instruction from outside of the buffer while the instruction is re-executed, the restart instruction pointer configured to track an address following a last complete instruction held in the buffer.

19. The method of claim 18, where the buffer is configured to store a plurality of bundles of micro-operations, each micro-operation corresponding to one or more ISA instructions or parts of ISA instructions, where the restart instruction pointer is configured to track an address following a last complete instruction held in the buffer with reference to a boundary instruction pointer configured to track a boundary between a last bundle for a complete ISA instruction held in the buffer and a subsequent bundle belonging to an incomplete ISA instruction held in the buffer, and where fetching another instruction from outside the buffer comprises tracking a boundary between a last bundle for a complete ISA instruction held in the buffer and a subsequent bundle belonging to an incomplete ISA instruction held in the buffer with the boundary instruction pointer.

20. A microprocessor including scheduler logic, the scheduler logic comprising:

a buffer for storing a plurality of bundles of micro-operations in a checkpointed state during runahead, each micro-operation corresponding to one or more ISA instructions held in the buffer for dispatch to an execution mechanism of the microprocessor for execution upon re-entering after runahead, at least one of the ISA instructions having been previously dispatched to the execution mechanism;

a boundary instruction pointer for tracking a boundary between a last bundle for a last complete ISA instruction held in the buffer and a subsequent bundle belonging to an incomplete ISA instruction held in the buffer; and

a restart instruction pointer for tracking an address following a last complete instruction held in the buffer, the restart instruction pointer directing an instruction pointer for fetch logic so that the fetch logic fetches another instruction from outside of the buffer while the one or more ISA instructions held in the buffer are re-dispatched for re-execution.