CHECKPOINTED BUFFER FOR RE-ENTRY FROM RUNAHEAD
First Claim
1. A microprocessor, comprising:
- fetch logic;
one or more execution mechanisms for executing a retrieved instruction provided by the fetch logic; and
scheduler logic for scheduling the retrieved instruction for execution, the scheduler logic including a buffer for storing the retrieved instruction and one or more additional instructions, the scheduler logic being configured, upon the microprocessor re-entering at a particular execution location after runahead, to re-dispatch, from the buffer, an instruction that has been previously dispatched to one of the execution mechanisms.
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Abstract
Embodiments related to re-dispatching an instruction selected for re-execution from a buffer upon a microprocessor re-entering a particular execution location after runahead are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic, one or more execution mechanisms for executing a retrieved instruction provided by the fetch logic, and scheduler logic for scheduling the retrieved instruction for execution. The example scheduler logic includes a buffer for storing the retrieved instruction and one or more additional instructions, the scheduler logic being configured, upon the microprocessor re-entering at a particular execution location after runahead, to re-dispatch, from the buffer, an instruction that has been previously dispatched to one of the execution mechanisms.
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Citations
20 Claims
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1. A microprocessor, comprising:
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fetch logic; one or more execution mechanisms for executing a retrieved instruction provided by the fetch logic; and scheduler logic for scheduling the retrieved instruction for execution, the scheduler logic including a buffer for storing the retrieved instruction and one or more additional instructions, the scheduler logic being configured, upon the microprocessor re-entering at a particular execution location after runahead, to re-dispatch, from the buffer, an instruction that has been previously dispatched to one of the execution mechanisms. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for re-dispatching an instruction to be re-executed at a microprocessor, the method comprising:
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reading an instruction selected for re-execution upon the microprocessor re-entering a particular execution location after runahead, the instruction held in a buffer for re-dispatch to one or more execution mechanisms of the microprocessor; after reading the selected instruction, re-dispatching the instruction; and from outside of the buffer, fetching another instruction while the selected instruction is re-executed. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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20. A microprocessor including scheduler logic, the scheduler logic comprising:
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a buffer for storing a plurality of bundles of micro-operations in a checkpointed state during runahead, each micro-operation corresponding to one or more ISA instructions held in the buffer for dispatch to an execution mechanism of the microprocessor for execution upon re-entering after runahead, at least one of the ISA instructions having been previously dispatched to the execution mechanism; a boundary instruction pointer for tracking a boundary between a last bundle for a last complete ISA instruction held in the buffer and a subsequent bundle belonging to an incomplete ISA instruction held in the buffer; and a restart instruction pointer for tracking an address following a last complete instruction held in the buffer, the restart instruction pointer directing an instruction pointer for fetch logic so that the fetch logic fetches another instruction from outside of the buffer while the one or more ISA instructions held in the buffer are re-dispatched for re-execution.
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Specification