SEMICONDUCTOR STORAGE DEVICE, METHOD OF CONTROLLING THE SAME, AND ERROR CORRECTION SYSTEM

• US 20130297984A1
• Filed: 07/11/2013
• Published: 11/07/2013
• Est. Priority Date: 02/29/2008
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yamaga, Akira
• Granted Patent: US 8,751,896 B2
• Time in Patent Office: Days
• US Class Current: 714/755
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: H03M 13/29 combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence

Abstract

A semiconductor storage device, a method of controlling the same, and an error correction system allow reduction in power consumption and circuit scale without detriment to error correction capability. An error correction code (ECC) circuit of a solid state drive (SSD) performs first error correction on read data using a first error correction code (Hamming code), and further performs second error correction on the result of the first error correction using a second error correction code (BHC code).

Furthermore, the ECC circuit performs third error correction on the result of the second error correction using a third error correction code (RS code).

Claims

1. A semiconductor storage device comprising:

a first error-correction-code generating unit that generates a first error correction code for each first unit data included in first data and for first unit data included in second data;

a second error-correction-code generating unit that generates a second error correction code for a set of data which includes at least one first unit data from first data and one first unit data from second data; and

a memory that can store therein at least the first data and second data.

2. The semiconductor storage device according to claim 1, wherein levels of error correction capabilities are provided in a descending order where the second error correction code is greater than the first error correction code.

3. The semiconductor storage device according to claim 1, further comprising an error-detection-code generating unit that generates an error detection code for first unit data included in first data and for first unit data included in second data.

4. The semiconductor storage device according to claim 1, wherein the memory comprises a first group of memory cells and a first word line, and the first group of memory cells being commonly connected to the first word line, wherein first data and first error correction code each generated for first data are stored in the first group of memory cells.

5. The semiconductor storage device according to claim 1, further comprising:

a first error correcting unit that performs a first error correction process, using the first error correction code, on the first unit data included in first data for which the first error correction code is generated; and

a second error correcting unit that performs a second error correction process, using the second error correction code, on the set of data for which the second error correction code is generated.

6. The semiconductor storage device according to claim 5, wherein the first error correcting unit and the second error correcting unit alternately repeat respective error correction processes.

7. The semiconductor storage device according to claim 1, wherein the first error correction code is a BCH code and the second error correction code is an RS code.