THIN-FILM SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20130299837A1
• Filed: 07/12/2013
• Published: 11/14/2013
• Est. Priority Date: 11/17/2011
• Status: Active Grant

• Current Assignee: Panasonic Intellectual Property Corporation of America (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation), Panasonic Liquid Crystal Display Company Limited (Panasonic Holdings Corporation)
• Inventors: HAYASHI, Hiroshi, KAWASHIMA, Takahiro, KAWACHI, Genshiro
• Granted Patent: US 9,166,056 B2
• Time in Patent Office: Days
• US Class Current: 257/66
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78636 with supplementary region or layer for improving the flatness of the device
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate

Abstract

In a thin-film semiconductor device, a semiconductor layer has a bandgap energy of 1.6 eV or less, an insulating layer formed above the semiconductor layer includes: a first insulating layer region placed outside of a first contact opening and above one end of a gate electrode; a second insulating layer region placed outside of a second contact opening and above the other end of the gate electrode which opposes the one end; and a third insulating layer region being rectangular and placed between the first contact opening and the second contact opening.

Claims

1. A thin-film semiconductor device comprising:

a substrate;

a gate electrode formed above the substrate;

a gate insulating film formed above the gate electrode and above the substrate extending beyond both ends of the gate electrode;

a semiconductor layer formed above the gate insulating film, and having a channel region and a bandgap energy of 1.6 eV or less;

an insulating layer formed above the semiconductor layer, having a first contact opening and a second contact opening that are placed apart from each other, and including a first insulating layer region, a second insulating layer region, and a third insulating layer region that is rectangular, the first insulating layer region being placed outside of the first contact opening and above one end of the gate electrode, the second insulating layer region being placed outside of the second contact opening and above the other end of the gate electrode which opposes the one end, and the third insulating layer region being placed between the first contact opening and the second contact opening; and

a source electrode and a drain electrode both formed above the insulating layer, the source electrode being electrically connected to the channel region with the first contact opening therebetween, and the drain electrode opposing the source electrode and being electrically connected to the channel region with the second contact opening therebetween,

wherein each of the source electrode and the drain electrode has a size in a channel width direction greater than a size of the third insulating layer region in the channel width direction, and the third insulating layer region has corners each of which is below a corresponding one of the source electrode and the drain electrode.

2. The thin-film semiconductor device according to claim 1,

wherein the third insulating layer region serves as a channel etching stopper layer that covers the channel region.

3. The thin-film semiconductor device according to claim 1,

wherein each end of the source electrode and the drain electrode protrudes 2 μ

m or more from both ends of the third insulating layer region in the channel width direction.

4. The thin-film semiconductor device according to claim 1,

wherein each end of the source electrode and the drain electrode protrudes 4 μ

m or more from both ends of the third insulating layer region in the channel width direction.

5. A method of manufacturing a thin-film semiconductor device, the method comprising:

preparing a substrate;

forming a gate electrode above the substrate;

forming a gate insulating film above the gate electrode and above the substrate extending beyond both ends of the gate electrode;

forming, above the gate insulating film, a semiconductor layer having a channel region and a bandgap energy of 1.6 eV or less;

forming an insulating layer above the semiconductor layer;

forming, in the insulating layer, a first contact opening and a second contact opening apart from each other so that the insulating layer includes a first insulating layer region, a second insulating layer region, and a third insulating layer region that is rectangular, the first insulating layer region being placed outside of the first contact opening and above one end of the gate electrode, the second insulating layer region being placed outside of the second contact opening and above the other end of the gate electrode which opposes the one end, and the third insulating layer region being placed between the first contact opening and the second contact opening; and

forming, above the insulating layer, a source electrode and a drain electrode that opposes the source electrode, the source electrode being electrically connected to the channel region with the first contact opening therebetween, and the drain electrode being electrically connected to the channel region with the second contact opening therebetween,

wherein each of the source electrode and the drain electrode has a size in a channel width direction greater than a size of the third insulating layer region in the channel width direction, and the third insulating layer region has corners each of which is below a corresponding one of the source electrode and the drain electrode.