Semiconductor Device and Method of Forming Interposer with Opening to Contain Semiconductor Die

• US 20130299982A1
• Filed: 07/17/2013
• Published: 11/14/2013
• Est. Priority Date: 09/23/2009
• Status: Abandoned Application

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Stats Chippac Limited
• Inventors: Pagaila, Reza A., Lin, Yaojian, Koo, Jun Mo, Chi, HeeJo
• Application Number:
  US13/944,825
• Publication Number:
  US 20130299982A1
• Time in Patent Office: Days
• US Class Current: 257/738
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48157 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48158 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/4816 connecting the wire to a pin of the item
• CPC Class Codes: H01L 2224/73203 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73259 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/81001 : involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/812 : Applying energy for connecting
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/157 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die.

Claims

1. A method of making a semiconductor device, comprising:

providing a carrier;

forming an interface layer over the carrier;

disposing a first substrate over the carrier;

disposing a second substrate over the carrier;

disposing a first semiconductor die over the first and second substrates electrically connected to the first and second substrates;

depositing an encapsulant over the first semiconductor die and over the first and second substrates; and

removing the carrier and interface layer.

2. The method of claim 1, further including forming a plurality of bumps over the first and second substrates.

3. The method of claim 1, wherein disposing the first and second substrates includes simultaneously disposing the first and second substrates over the carrier.

4. The method of claim 1, further including forming an electrical connection between the first and second substrates.

5. The method of claim 1, further including forming an interconnect structure over a surface of the first substrate opposite the first semiconductor die.

6. The method of claim 1, further including disposing a second semiconductor die over the first substrate.

7. A method of making a semiconductor device, comprising:

providing a first substrate;

disposing a second substrate adjacent to the first substrate;

disposing a first semiconductor die over the first substrate electrically connected to the first substrate; and

depositing an encapsulant over the first semiconductor die and over the first and second substrates.

8. The method of claim 7, further including forming a bump between the first semiconductor die and first substrate.

9. The method of claim 7, further including disposing a passive component over the first or second substrate.

10. The method of claim 7, further including forming an interconnect structure over a surface of the first substrate opposite the first semiconductor die.

11. The method of claim 7, further including forming an electrical connection between the first and second substrates.

12. The method of claim 7, further including forming a bump over a surface of the first substrate opposite the first semiconductor die.

13. The method of claim 7, further including disposing a second semiconductor die over the first semiconductor die.

14. A semiconductor device, comprising:

a first substrate;

a second substrate;

a first semiconductor die disposed over the first and second substrates; and

an encapsulant deposited over the first semiconductor die and over the first and second substrates.

15. The semiconductor device of claim 14, further including a bump formed between the first semiconductor die and the second substrate.

16. The semiconductor device of claim 14, wherein the first substrate includes a laminate interposer.

17. The semiconductor device of claim 14, wherein the first substrate includes a coefficient of thermal expansion (CTE) similar to a CTE of the semiconductor die.

18. The semiconductor device of claim 14, wherein the first semiconductor die includes a ball grid array.

19. The semiconductor device of claim 14, further including a second semiconductor die disposed over the first substrate.

20. A semiconductor device, comprising:

a first substrate;

a second substrate; and

a first semiconductor die disposed over the first and second substrates and electrically connected to the first and second substrates.

21. The semiconductor device of claim 20, further including a second semiconductor die disposed over the first substrate.

22. The semiconductor device of claim 20, wherein the first substrate includes a laminate interposer.

23. The semiconductor device of claim 20, wherein the second substrate includes an insulating layer and a conductive layer.

24. The semiconductor device of claim 20, wherein the first substrate includes a coefficient of thermal expansion (CTE) similar to a CTE of the semiconductor die.

25. The semiconductor device of claim 20, further including a passive component disposed over the first substrate.