SEMICONDUCTOR STRUCTURE HAVING ETCH STOP LAYER

• US 20130299987A1
• Filed: 07/24/2013
• Published: 11/14/2013
• Est. Priority Date: 08/18/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LIN, Mei-Hsuan, LIN, Chih-Hsun, CHAO, Chih-Kang, WANG, Ling-Sung
• Granted Patent: US 8,836,088 B2
• Time in Patent Office: Days
• US Class Current: 257/741
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76822 Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor structure includes a substrate, a conductive feature over the substrate, a conductive plug structure contacting a portion of an upper surface of the conductive feature, a first etch stop layer over another portion of the upper surface of the conductive feature, and a second etch stop layer over the first etch stop layer. The first etch stop layer is a doped etch stop layer. The first etch stop layer is to function as an etch stop layer during a predetermined etching process for etching the second etch stop layer.

Claims

1. A semiconductor structure, comprising:

a substrate;

a conductive feature over the substrate;

a conductive plug structure contacting a portion of an upper surface of the conductive feature;

a first etch stop layer over another portion of the upper surface of the conductive feature, the first etch stop layer being a doped etch stop layer; and

a second etch stop layer over the first etch stop layer, the first etch stop layer being configured to function as an etch stop layer during a predetermined etching process for etching the second etch stop layer.

2. The semiconductor structure of claim 1, wherein the first etch stop layer comprises carbon-doped silicon oxide.

3. The semiconductor structure of claim 1, wherein the conductive feature comprises metal silicide.

4. The semiconductor structure of claim 1, wherein the first etch stop layer has a thickness ranging from 5 to 40 angstroms.

5. The semiconductor structure of claim 1, wherein the first etch stop layer comprises silicon oxide doped with carbon, nitride, hydrogen, indium, germanium, or a combination thereof.

6. The semiconductor structure of claim 1, wherein the second etch stop layer comprises silicon nitride or silicon oxynitride.

7. The semiconductor structure of claim 1, wherein the second etch stop layer has a thickness ranging from 200 to 800 angstroms.

8. The semiconductor structure of claim 1, further comprising a dielectric layer formed over the second etch stop layer and surrounding the conductive plug structure.

9. The semiconductor structure of claim 1, further comprising a buffer layer between the another portion of the upper surface of the conductive feature and the first etch stop layer.

10. The semiconductor structure of claim 9, wherein the buffer layer has a thickness ranging from 10 to 90 angstroms.

11. The semiconductor structure of claim 9, wherein the buffer layer comprises silicon oxide.

12. A manufacture, comprising:

a substrate;

a conductive feature over the substrate;

a conductive plug structure on a portion of an upper surface of the conductive feature;

a first etch stop layer over another portion of the upper surface of the conductive feature, the first etch stop layer comprising a first material and further doped with a second material;

a second etch stop layer over the first etch stop layer, the first etch stop layer and the second stop layer being configured to have a selectivity characteristic during a predetermined etching process for etching the second etch stop layer; and

a dielectric layer over the second etch stop layer and surrounding the conductive plug structure.

13. The manufacture of claim 12, further comprising a buffer layer between the another portion of the upper surface of the conductive feature and the first etch stop layer, the buffer layer comprising the first material.

14. The manufacture of claim 13, wherein the buffer layer has a thickness ranging from 10 to 90 angstroms.

15. The manufacture of claim 12, wherein the first material comprises silicon oxide, and the second material comprises carbon, nitride, hydrogen, indium, germanium, or a combination thereof.

16. The manufacture of claim 12, wherein the first etch stop layer has a thickness ranging from 5 to 40 angstroms.

17. The manufacture of claim 12, wherein the second etch stop layer comprises silicon nitride or silicon oxynitride.

18. The manufacture of claim 12, wherein the second etch stop layer has a thickness ranging from 200 to 800 angstroms.

19. A manufacture, comprising:

a substrate;

a conductive feature over the substrate;

a conductive plug structure on a portion of an upper surface of the conductive feature;

a buffer layer on another portion of the upper surface of the conductive feature;

a first etch stop layer on the buffer layer, the buffer layer and the first stop layer being configured to have a first selectivity characteristic during a first etching process for etching the first etch stop layer; and

a second etch stop layer on the first etch stop layer, the first etch stop layer and the second stop layer being configured to have a second selectivity characteristic during a second etching process for etching the second etch stop layer.

20. The manufacture of claim 19, wherein the buffer layer comprises a dielectric material, and the first etch stop layer comprises the dielectric material doped with carbon, nitride, hydrogen, indium, germanium, or a combination thereof.