SEMICONDUCTOR DEVICE

• US 20130301332A1
• Filed: 05/08/2013
• Published: 11/14/2013
• Est. Priority Date: 05/11/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Onuki, Tatsuya
• Granted Patent: US 9,001,549 B2
• Time in Patent Office: Days
• US Class Current: 365/72
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/10 for interconnecting capacitors

Abstract

To provide a semiconductor device with high reliability in operation, in which data in a volatile memory can be saved to a non-volatile memory. For example, the semiconductor device includes an SRAM provided with first and second data storage portions and a non-volatile memory provided with third and fourth data storage portions. The first data storage portion is electrically connected to the fourth data storage portion through a transistor, and the second data storage portion is electrically connected to the third data storage portion through a transistor. The transistors are turned off when the SRAM operates, and the transistors are turned on when the SRAM does not operate, so that data in the SRAM is saved to the non-volatile memory. Precharge is performed when the SRAM is restored.

Claims

1. A semiconductor device comprising a plurality of memory elements arranged in a matrix, each memory element including:

a first memory circuit comprising a first data storage portion and a second data storage portion; and

a second memory circuit comprising a third data storage portion and a fourth data storage portion,

wherein the first data storage portion is electrically connected to a bit line through a first transistor;

wherein the second data storage portion is electrically connected to an inverted bit line through a second transistor;

wherein the first transistor and the second transistor are electrically connected to a first word line;

wherein the third data storage portion is electrically connected to the second data storage portion through a third transistor;

wherein the fourth data storage portion is electrically connected to the first data storage portion through a fourth transistor;

wherein the third transistor and the fourth transistor are electrically connected to a second word line;

wherein the third data storage portion is electrically connected to one electrode of a first capacitor;

wherein the fourth data storage portion is electrically connected to one electrode of a second capacitor;

wherein the other electrodes of the first capacitor and the second capacitor are electrically connected to a low potential power source line;

wherein the second memory circuit is configured to save data in the first data storage portion and the second data storage portion to the third data storage portion and the fourth data storage portion immediately before supply of power to the first memory circuit is stopped; and

wherein the first data storage portion and the second data storage portion are configured to be precharged in restoring the first memory circuit, thereby reading data from the third data storage portion and the fourth data storage portion to the first data storage portion and the second data storage portion.

3. The semiconductor device according to claim 1, wherein the first data storage portion and the second data storage portion are precharged to a potential intermediate between a potential of a high potential power source line and a potential of the low potential power source line.

5. The semiconductor device according to claim 3, wherein the low potential power source line has a ground potential.

7. The semiconductor device according to claim 1, wherein each of the first transistor and the second transistor includes a silicon region.

9. The semiconductor device according to claim 1, wherein each of the third transistor and the fourth transistor includes an oxide semiconductor region.

11. The semiconductor device according to claim 1, wherein the third transistor and the fourth transistor are provided over the first transistor and the second transistor.

13. An electronic device using the semiconductor device according to claim 1.

2. A semiconductor device comprising a plurality of memory elements arranged in a matrix, each memory element including:

a first memory circuit comprising a first data storage portion and a second data storage portion; and

a second memory circuit comprising a third data storage portion,

wherein the first data storage portion is electrically connected to a bit line through a first transistor;

wherein the second data storage portion is electrically connected to an inverted bit line through a second transistor;

wherein the first transistor and the second transistor are electrically connected to a first word line;

wherein the third data storage portion is electrically connected to the second data storage portion through a third transistor;

wherein the third transistor is electrically connected to a second word line;

wherein the third data storage portion is electrically connected to one electrode of a capacitor;

wherein the other electrode of the capacitor is electrically connected to a low potential power source line;

wherein the second memory circuit is configured to save data in the second data storage portion to the third data storage portion immediately before supply of power to the first memory circuit is stopped; and

wherein the first data storage portion and the second data storage portion are configured to be precharged in restoring the first memory circuit, thereby reading data from the third data storage portion to the second data storage portion.

4. The semiconductor device according to claim 2, wherein the first data storage portion and the second data storage portion are precharged to a potential intermediate between a potential of a high potential power source line and a potential of the low potential power source line.

6. The semiconductor device according to claim 4, wherein the low potential power source line has a ground potential.

8. The semiconductor device according to claim 2, wherein each of the first transistor and the second transistor includes a silicon region.

10. The semiconductor device according to claim 2, wherein the third transistor includes an oxide semiconductor region.

12. The semiconductor device according to claim 2, wherein the third transistor is provided over the first transistor and the second transistor.

14. An electronic device using the semiconductor device according to claim 2.