Method, System, and Apparatus for Dynamic Reconfiguration of Resources

• US 20130304957A1
• Filed: 11/02/2012
• Published: 11/14/2013
• Est. Priority Date: 12/13/2004
• Status: Active Grant

• Current Assignee: Akhilesh Kumar, Doddaballapur Jayasimha, Eric Richard Delano, Ioanns Y. Schoinas, Jose A. Vargas, Mani Ayyar
• Original Assignee: Akhilesh Kumar, Doddaballapur Jayasimha, Eric Richard Delano, Ioanns Y. Schoinas, Jose A. Vargas, Mani Ayyar
• Inventors: Ayyar, Mani, Delano, Eric Richard, Kumar, Akhilesh, Jayasimha, Doddaballapur, Vargas, Jose A., Schoinas, Ioanns Y.
• Granted Patent: US 9,223,738 B2
• Time in Patent Office: Days
• US Class Current: 710/260
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4081 Live connection to bus, e.g. hot-plugging current or voltage limitation during live insertion H02H9/004
• CPC Class Codes: G06F 13/409 Mechanical coupling back panels H05K7/1438
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files
• CPC Class Codes: G06F 9/50 Allocation of resources, e.g. of the central processing unit [CPU]
• CPC Class Codes: G06F 9/5011 the resources being hardware resources other than CPUs, Servers and Terminals

Abstract

A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

Claims

1-2. -2. (canceled)

3. An apparatus comprising:

input/output (“

I/O”

) logic coupled to a point-to-point interconnect capable of coupling caching agents and home agents, the I/O logic including a physical layer to receive an operation based on an interrupt generated in response to an insertion of a resource into a computing system, wherein, in response to the physical layer receiving the operation, the I/O logic to enter a state where no protocol transactions are generated, and wherein during state routing, tables associated with the resource are updated without rebooting an operating system (“

OS”

) of the computing system.

4. The apparatus of claim 3, wherein if multiple resources are added to multiple OS partitions, multiple interrupts are sent to the multiple OS partitions.

5. The apparatus of claim 3, wherein the caching agents and the home agents are coupled to a network fabric adhered to layered protocol scheme and used for transporting messages from one protocol to another protocol, wherein the network fabric includes one or more of a link layer, a physical layer, a protocol layer, a routing layer, and a transport layer.

6. The apparatus of claim 3, wherein the resource comprises a processor node, a memory-only node, or an I/O hub node.

7. A method comprising

generating an interrupt in response to an insertion of a resource into a computing system;

receiving, at a physical layer of an input/output logic, an operation based on the interrupt, wherein the I/O logic is coupled to a point-to-point interconnect capable of coupling caching agents and home agents;

in response to the physical layer receiving the operation, entering the I/O logic into a state where no protocol transactions are generated; and

propagating the interrupt to the operating system (“

OS”

) level through a dynamic update without having to restart the OS, wherein propagating includes during state routing, updating tables associated with the resource without rebooting the operating system.

8. The method of claim 7, wherein if multiple resources are added to multiple OS partitions, multiple interrupts are sent to the multiple OS partitions.

9. The method of claim 7, wherein the caching agents and the home agents are coupled to a network fabric adhered to layered protocol scheme and used for transporting messages from one protocol to another protocol, wherein the network fabric includes one or more of a link layer, a physical layer, a protocol layer, a routing layer, and a transport layer.

10. The method of claim 7, wherein the resource comprises a processor node, a memory-only node, or an I/O hub node.

11. A system comprising:

a computing system having memory and a processing device coupled to the memory, the computing system further having input/output (“

I/O”

) logic coupled to a point-to-point interconnect capable of coupling caching agents and home agents, the I/O logic including a physical layer to receive an operation based on an interrupt generated in response to an insertion of a resource into the computing system, wherein, in response to the physical layer receiving the operation, the I/O logic to enter a state where no protocol transactions are generated, and wherein during state routing, tables associated with the resource are updated without rebooting an operating system (“

OS”

) of the computing system.

12. The system of claim 11, wherein if multiple resources are added to multiple OS partitions, multiple interrupts are sent to the multiple OS partitions.

13. The system of claim 11, wherein the caching agents and the home agents are coupled to a network fabric adhered to layered protocol scheme and used for transporting messages from one protocol to another protocol, wherein the network fabric includes one or more of a link layer, a physical layer, a protocol layer, a routing layer, and a transport layer.

14. The system of claim 11, wherein the resource comprises a processor node, a memory-only node, or an I/O hub node.