DATA PROCESSING METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE DEVICE USING THE SAME
First Claim
1. A data processing method for a re-writable non-volatile memory module having a plurality of physical programming units, wherein each of the plurality of physical programming units has a data bit area and a redundancy bit area, the data bit area has a plurality of physical access addresses, a plurality of logical programming units is configured to map to at least a portion of the plurality of physical programming units, and each of the plurality of logical programming units has a plurality of logical access addresses, the data processing method comprising:
- receiving a first write data stream, wherein the first write data stream associates with a first logical access address among the plurality of logical access addresses, and the first logical access address associates with a first logical programming unit among the plurality of logical programming units;
selecting a first physical programming unit from the plurality of physical programming units;
determining whether the first write data stream associates with a pattern;
if the first write data stream does not associate with the pattern, setting identification information corresponding to the first logical access address as a default value, programming the first write data stream into the first logical access address among the plurality of logical access addresses in the data bit area of the first physical programming unit and storing the identification information corresponding to the first logical access address in a predetermined area;
if the first write data stream associates with the pattern, setting the identification information corresponding to the first logical access address as an identification value corresponding to the pattern, and storing the identification information corresponding to the first logical access address in the predetermined area, wherein the first write data stream is not programmed into the first physical programming unit; and
mapping the first logical programming unit to the first physical programming unit.
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Accused Products
Abstract
A data processing method for a re-writable non-volatile memory module is provided. The method includes receiving a write data stream associating to a logical access address of a logical programming unit; selecting a physical programming unit; and determining whether the write data stream associates with a kind of pattern. The method includes, if the write data stream associates with the kind of pattern, setting identification information corresponding to the logical access address as an identification value corresponding to the pattern, and storing the identification information corresponding to the logical access address into a predetermined area, wherein the write data stream is not programmed into the selected physical programming unit. The method further includes mapping the logical programming unit to the physical programming unit. Accordingly, the method can effectively shorten the time for writing data into the re-writable non-volatile memory module.
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Citations
26 Claims
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1. A data processing method for a re-writable non-volatile memory module having a plurality of physical programming units, wherein each of the plurality of physical programming units has a data bit area and a redundancy bit area, the data bit area has a plurality of physical access addresses, a plurality of logical programming units is configured to map to at least a portion of the plurality of physical programming units, and each of the plurality of logical programming units has a plurality of logical access addresses, the data processing method comprising:
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receiving a first write data stream, wherein the first write data stream associates with a first logical access address among the plurality of logical access addresses, and the first logical access address associates with a first logical programming unit among the plurality of logical programming units; selecting a first physical programming unit from the plurality of physical programming units; determining whether the first write data stream associates with a pattern; if the first write data stream does not associate with the pattern, setting identification information corresponding to the first logical access address as a default value, programming the first write data stream into the first logical access address among the plurality of logical access addresses in the data bit area of the first physical programming unit and storing the identification information corresponding to the first logical access address in a predetermined area; if the first write data stream associates with the pattern, setting the identification information corresponding to the first logical access address as an identification value corresponding to the pattern, and storing the identification information corresponding to the first logical access address in the predetermined area, wherein the first write data stream is not programmed into the first physical programming unit; and mapping the first logical programming unit to the first physical programming unit. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A data processing method for a re-writable non-volatile memory module having a plurality of physical programming units, wherein each of the plurality of physical programming units has a data bit area and a redundancy bit area, the data bit area has a plurality of physical access addresses, a plurality of logical programming units is configured to map to a portion of the plurality of physical programming units, and each of the plurality of logical programming units has a plurality of logical access addresses, the data processing method comprising:
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receiving a first write data stream, wherein the first write data stream associates with a first logical access address among the plurality of logical access addresses, and the first logical access address associates with a first logical programming unit among the plurality of logical programming units; selecting the a first physical programming unit from the plurality of physical programming units; determining whether the first write data stream associates with one of a plurality of patterns; if the first write data stream does not associate with any one of the plurality of pattern, setting identification information corresponding to the first logical access address as a default value, programming the first write data stream into a first physical access address among the plurality of physical access addresses in the data bit area of the first physical programming unit and programming the identification information corresponding to the first logical access address into the redundancy bit area of the first physical programming unit; if the first write data stream associates with one of the multiple patterns, setting the identification information corresponding to the first logical access address as an identification value and programming the identification information corresponding to the first logical access address into the redundancy bit area of the first physical programming unit, wherein the first write data stream is not programmed into the first physical programming unit; and mapping the first logical programming unit to the first physical programming unit. - View Dependent Claims (9)
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10. A memory controller for controlling a re-writable non-volatile memory module having a plurality of physical programming units, wherein each of the plurality of physical programming units has a data bit area and a redundancy bit area, the data bit area has a plurality of physical access addresses, the memory controller comprising:
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a host interface, configured to be coupled to a host system; a memory interface, configured to be coupled to a rewritable non-volatile memory module; and a memory management circuit, coupled to the host interface and the rewritable non-volatile memory module and configured to configure a plurality of logical programming units to map to at least a portion of the plurality of physical programming units, wherein each of the plurality of logical programming units has a plurality of logical access addresses, wherein the memory management circuit is further configured to receive a first write data stream from the host system, wherein the first write data stream associates with a first logical access address among the plurality of logical access addresses, and the first logical access address associates with a first logical programming unit among the plurality of logical programming units, wherein the memory management circuit is further configured to select a first physical programming unit from the plurality of physical programming units and determine whether the first write data stream associates with a pattern, wherein if the first write data stream does not associate with the pattern, the memory management circuit is further configured to set identification information corresponding to the first logical access address as a default value, program the first write data stream into a first physical access address among the plurality of physical access addresses in the data bit area of the first physical programming unit and store the identification information corresponding to the first logical access address in a predetermined area, wherein if the first write data stream associates with the pattern, the memory management circuit is further configured to set the identification information corresponding to the first logical access address as an identification value corresponding to the pattern and store the identification information corresponding to the first logical access address in the predetermined area, wherein the first write data stream is not programmed into the first physical programming unit, and wherein the memory management circuit is further configured to map the first logical programming unit to the first physical programming unit. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A memory storage device, comprising:
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a connector, configured to be coupled to a host system; a rewritable non-volatile memory module, having a plurality of physical programmed blocks, wherein each of the plurality of physical programming units has a data bit area and a redundancy bit area, and the data bit area has a plurality of physical access addresses; and a memory controller, coupled to the connector and the rewritable non-volatile memory module and configured to configure a plurality of logical programming units to be mapped to at least a portion of the plurality of physical programming units, wherein each of the plurality of logical programming units has a plurality of logical access addresses, wherein the memory controller is further configured to receive a first write data stream from the host system, wherein the first write data stream associates with a first logical access address among the plurality of logical access addresses, and the first logical access address associates with a first logical programming unit among the plurality of logical programming units, wherein the memory controller is further configured to select a first physical programming unit from the plurality of physical programming units and determine whether the first write data stream associates with a pattern, wherein if the first write data stream does not associate with the pattern, the memory controller is further configured to set identification information corresponding to the first logical access address as a default value, program the first write data stream into a first physical access address among the plurality of physical access addresses in the data bit area of the first physical programming unit and store the identification information corresponding to the first logical access address in a predetermined area, wherein if the first write data stream associates with the pattern, the memory controller is further configured to set the identification information corresponding to the first logical access address as an identification value corresponding to the pattern and store the identification information corresponding to the first logical access address in the predetermined area, wherein the first write data stream is not programmed into the first physical programming unit, and wherein the memory controller is further configured to map the first logical programming unit to the first physical programming unit. - View Dependent Claims (18, 19, 20, 21, 22, 23)
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24. A memory storage device, comprising:
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a connector, configured to be coupled to a host system; a rewritable non-volatile memory module, having a plurality of physical programmed blocks, wherein each of the plurality of physical programming units has a data bit area and a redundancy bit area, and the data bit area has a plurality of physical access addresses; and a memory controller, coupled to the connector and the rewritable non-volatile memory module and is configured to configure a plurality of logical programming units to be mapped to a portion of the plurality of physical programming units, wherein each of the plurality of logical programming units has a plurality of logical access addresses, wherein the memory controller is further configured to receive a first write data stream from the host system, wherein the first write data stream associates with a first logical access address among the plurality of logical access addresses, and the first logical access address associates with a first logical programming unit among the plurality of logical programming units, wherein the memory controller is further configured to select a first physical programming unit from the plurality of physical programming units and determine whether the first write data stream associates with a pattern among multiple patterns, wherein if the first write data stream does not associate with any one of the multiple patterns, the memory controller is further configured to set identification information corresponding to the first logical access address as a default value, program the first write data stream into a first physical access address among the plurality of physical access addresses in the data bit area of the first physical programming unit and program the identification information corresponding to the first logical access address into the redundancy bit area of the first physical programming unit; wherein if the first write data stream associates with one of the multiple patterns, the memory controller is further configured to set the identification information corresponding to the first logical access address as an identification value corresponding to the pattern and program the identification information corresponding to the first logical access address into the redundancy bit area of the first physical programming unit, wherein the first write data stream is not programmed into the first physical programming unit; and wherein the memory controller is further configured to map the first logical programming unit to the first physical programming unit. - View Dependent Claims (25)
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26. A data processing method for a re-writable non-volatile memory module having a plurality of physical programming units, wherein each of the plurality of physical programming units has a data bit area and a redundancy bit area, the data bit area has a plurality of physical access addresses, a plurality of logical programming units is configured to be mapped to at least a portion of the plurality of physical programming units, and each of the plurality of logical programming units has a plurality of logical access addresses, the data processing method comprising,
receiving a read command from a host system, wherein the read command instructs to read data stored in a first logical access address among the plurality of logical access addresses; -
reading identification information corresponding to the first logical access address from a predetermined area; determining whether the identification information is an identification value; transmitting a predetermined data the host system if the read identification information is the identification value; and transmitting a data stream read from a physical access address mapped to the first logical access address to the host system if the identification information is not the identification value, wherein the number of bits of the identification value is smaller than the number of bits of the predetermined data.
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Specification