SEMICONDUCTOR ACTIVE MATRIX ON BURIED INSULATOR

• US 20130306971A1
• Filed: 06/18/2012
• Published: 11/21/2013
• Est. Priority Date: 05/16/2012
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Bedell, Stephen W., Hekmatshoartabari, Bahman, Sadana, Devendra K., Shahidi, Ghavam G., Shahrjerdi, Davood
• Granted Patent: US 8,610,212 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate

Abstract

A high resolution active matrix backplane is fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed on a semiconductor-on-insulator substrate. The backplane layer is spalled from the substrate. A frontplane layer including passive devices such as LCDs, OLEDs, photosensitive materials, or piezo-electric materials is formed over the backplane layer to form an active matrix structure. The active matrix structure may be fabricated to allow bottom emission and provide mechanical flexibility.

Claims

1. A structure comprising:

a semiconductor-on-insulator wafer, the wafer including a support substrate and a buried insulator layer;

a backplane including an array of transistors formed on the wafer;

an insulating layer formed on the backplane, wherein the backplane, the insulating layer and a wafer portion above the support substrate comprise a first backplane structure;

a metal layer formed on the first backplane structure, and

a flexible handle substrate bonded to the metal layer,

wherein the insulating layer has sufficient adhesion to the wafer and a fracture toughness value to allow spalling the first backplane structure, the metal layer and a residual layer from the support substrate by exerting a force on the metal layer via the flexible handle substrate.

4. The structure of claim 1, wherein the buried insulator layer includes a buried oxide layer having a thickness between 10-500 nm.

5. The structure of claim 4, wherein the buried oxide layer comprises silicon dioxide.

6. The structure of claim 1, wherein the backplane comprises a plurality of thin film transistors and capacitors.

2-3. -3. (canceled)

7-9. -9. (canceled)

19. An active matrix structure comprising:

a substrate including a buried insulator layer and a semiconductor layer adjoining the buried insulator layer;

a backplane layer formed on the substrate, the backplane layer including an array of active semiconductor devices;

an insulating layer formed on the backplane layer, the insulating layer including one or more vias;

a transparent conductive material layer adjoining the insulating layer and electrically contacting the backplane layer;

a frontplane layer formed on the transparent conductive material layer and including a plurality of passive devices such that the passive devices are addressable by the active semiconductor devices in the backplane, and

an encapsulation layer formed on the frontplane layer.

20. The active matrix structure of claim 19, wherein the buried insulator layer is transparent and the transparent conductive material layer directly contacts the buried insulator layer and is functional as a bottom electrode for the passive devices in the frontplane layer.

21. The active matrix structure of claim 19, wherein the encapsulation layer is flexible.

22. The active matrix structure of claim 19, wherein the active semiconductor devices include thin film transistors.

23. The active matrix structure of claim 19, wherein the passive devices include organic light emitting diodes.

24. The active matrix structure of claim 19, further including an antireflective coating or a polarizing film on the buried insulator layer.

25. The active matrix structure of claim 19, wherein the buried insulator layer is transparent and the encapsulation layer is flexible, the buried insulator layer has a thickness between 10-500 nm and the semiconductor layer has a thickness between 3 nm-30 μ

m, and the active semiconductor devices include thin film transistors and capacitors.