MANUFACTURING METHOD OF THIN FILM TRANSISTOR ARRAY PANEL

• US 20130306974A1
• Filed: 07/26/2013
• Published: 11/21/2013
• Est. Priority Date: 02/07/2011
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: PARK, Jeong Min, Woo, Dong-Won, Park, Je Hyeong, Kim, Sang Gab, Lee, Jung-Soo, Kim, Ji-Hyun
• Granted Patent: US 9,006,742 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78645 with multiple gate

Abstract

A manufacturing method of a thin film transistor array panel includes: simultaneously forming a gate conductor and a first electrode on a substrate, using a non-peroxide-based etchant; forming a gate insulating layer on the gate conductor and the first electrode; forming a semiconductor, a source electrode, and a drain electrode on the gate insulating layer; forming a passivation layer on the semiconductor, the source electrode, and the drain electrode; and forming a second electrode layer on the passivation layer.

Claims

1. A thin film transistor array panel comprising:

a substrate;

a gate conductor comprising a lower layer disposed on the substrate and an upper layer disposed on the lower layer;

a first electrode disposed on the substrate;

a gate insulating layer disposed on the gate conductor and the first electrode;

a semiconductor disposed on the gate insulating layer;

a source electrode and a drain electrode disposed on the semiconductor;

a passivation layer disposed on the source electrode and the drain electrode; and

a second electrode disposed on the passivation layer,

wherein, the lower layer of the gate conductor and the first electrode are disposed directly on the same layer and comprise the same type of material.

2. The thin film transistor array panel of claim 1, wherein the first electrode is a reference electrode and the second electrode is a pixel electrode.

3. The thin film transistor array panel of claim 2, wherein the upper layer of the gate conductor comprises copper or a copper alloy.

4. The thin film transistor array panel of claim 3, wherein the lower layer of the gate conductor and the first electrode comprise indium tin oxide (ITO) or indium zinc oxide (IZO).

5. The thin film transistor array panel of claim 1, wherein the first electrode is a pixel electrode and the second electrode is a reference electrode.

6. The thin film transistor array panel of claim 5, wherein the upper layer of the gate conductor comprises copper or a copper alloy.

7. The thin film transistor array panel of claim 6, wherein the lower layer of the gate conductor and the first electrode comprise indium tin oxide (ITO) or indium zinc oxide (IZO).