SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME

• US 20130306983A1
• Filed: 02/01/2012
• Published: 11/21/2013
• Est. Priority Date: 02/02/2011
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Nakano, Yuki, Nakamura, Ryota
• Granted Patent: US 9,136,322 B2
• Time in Patent Office: Days
• US Class Current: 257/76
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0607 for preventing surface leakage or controlling electric field concentration
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device according to the present invention includes a semiconductor layer made of a wide bandgap semiconductor having a gate trench provided with a sidewall and a bottom wall, a gate insulating film formed on the sidewall and the bottom wall of the gate trench, and a gate electrode embedded in the gate trench to be opposed to the semiconductor layer through the gate insulating film, while the semiconductor layer includes a first conductivity type source region formed to be exposed on the side of a front surface of the semiconductor layer for partially forming the sidewall of the gate trench, a second conductivity type body region formed on a side of the source region closer to a rear surface of the semiconductor layer to be in contact with the source region for partially forming the sidewall of the gate trench, a first conductivity type drift region formed on a side of the body region closer to the rear surface of the semiconductor layer to be in contact with the body region for forming the bottom wall of the gate trench, and a second conductivity type first breakdown voltage holding region selectively formed on an edge portion of the gate trench where the sidewall and the bottom wall intersect with each other in a partial region of the gate trench.

Claims

1. A semiconductor device comprising:

a semiconductor layer made of a wide bandgap semiconductor having a gate trench provided with a sidewall and a bottom wall;

a gate insulating film formed on the sidewall and the bottom wall of the gate trench; and

a gate electrode embedded in the gate trench to be opposed to the semiconductor layer through the gate insulating film, wherein

the semiconductor layer includes;

a first conductivity type source region formed to be exposed on the side of a front surface of the semiconductor layer for partially forming the sidewall of the gate trench;

a second conductivity type body region formed on a side of the source region closer to a rear surface of the semiconductor layer to be in contact with the source region for partially forming the sidewall of the gate trench;

a first conductivity type drift region formed on a side of the body region closer to the rear surface of the semiconductor layer to be in contact with the body region for forming the bottom wall of the gate trench; and

a second conductivity type first breakdown voltage holding region selectively formed on an edge portion of the gate trench where the sidewall and the bottom wall intersect with each other in a partial region of the gate trench.

2. The semiconductor device according to claim 1, wherein

the impurity concentration in the first breakdown voltage holding region is higher than the impurity concentration in the drift region.

3. The semiconductor device according to claim 1, wherein

the gate trench is formed in a latticed manner,

the semiconductor layer includes a plurality of unit cells partitioned by the latticed gate trench and provided in the form of polygonal prisms each having a plurality of corner portions, and each unit cell has the source region, the body region and the drift region, and

the first breakdown voltage holding region is selectively formed on a corner edge portion of the gate trench formed on the corner portion of the unit cell.

4. The semiconductor device according to claim 3, wherein

the first breakdown voltage holding region is formed to reach a portion of the body region immediately above the corner edge portion.

5. The semiconductor device according to claim 3, wherein

the first breakdown voltage holding region is selectively formed on an intersection portion of the latticed gate trench.

6. The semiconductor device according to claim 3, wherein

the semiconductor layer further includes a second conductivity type second breakdown voltage holding region, formed on a bottom wall of a linear portion of the latticed gate trench, having a width narrower than the width of the linear portion.

7. The semiconductor device according to claim 6, wherein

the impurity concentration in the second breakdown voltage holding region is higher than the impurity concentration in the first breakdown voltage holding region.

8. The semiconductor device according to claim 6, wherein

the thickness of the second breakdown voltage holding region is smaller than the thickness of the first breakdown voltage holding region.

9. The semiconductor device according to claim 1, wherein

the semiconductor layer further includes:

a source trench having a sidewall and a bottom wall, passing through the source region and the body region from the front surface and reaching the drift region; and

a second conductivity type third breakdown voltage holding region selectively formed on an edge portion of the source trench where the sidewall and the bottom wall intersect with each other in a partial region of the source trench.

10. The semiconductor device according to claim 1, wherein

the drift region includes:

a first region of a first impurity concentration forming the bottom wall of the gate trench; and

a second region of a second impurity concentration smaller than the first impurity concentration formed on a side of the first region closer to the rear surface of the semiconductor layer to be in contact with the first region.

11. The semiconductor device according to claim 10, wherein

the thickness of the first region is greater than the thickness of the first breakdown voltage holding region.

12. The semiconductor device according to claim 10, wherein

the thickness of the first region is not more than the thickness of the first breakdown voltage holding region.

13. The semiconductor device according to claim 10, wherein

the interface between the first region and the second region undulates in response to a step caused by partial lowering of the front surface of the semiconductor layer resulting from the formation of the gate trench.

14. The semiconductor device according to claim 10, wherein

the interface between the first region and the second region is at a constant distance from the front surface of the semiconductor layer.

15. The semiconductor device according to claim 1, wherein

a portion of the gate insulating film on the bottom wall of the gate trench is thicker than a portion of the gate insulating film on the sidewall of the gate trench, and a top portion thereof is below the deepest portion of the body region.

16. The semiconductor device according to claim 1, wherein

the front surface of the semiconductor layer is a C plane.

17. The semiconductor device according to claim 1, wherein

the body region is formed by ion implantation.

18. A method for producing a semiconductor device, comprising the steps of:

forming a semiconductor layer, which is a semiconductor layer made of a wide bandgap semiconductor, including a first conductivity type source region formed to be exposed on the side of a front surface thereof, a second conductivity type body region formed on a side of the source region closer to a rear surface to be in contact with the source region, and a first conductivity type drift region formed on a side of the body region closer to the rear surface to be in contact with the body region;

forming a gate trench having a sidewall and a bottom wall, passing through the source region and the body region from the front surface of the semiconductor layer and reaching the drift region; and

selectively implanting a second conductivity type impurity into an edge portion of the gate trench where the sidewall and the bottom wall intersect with each other in a partial region of the gate trench.

19. The method for producing a semiconductor device according to claim 18, further comprising a step of forming a first region of a first impurity concentration forming the bottom wall of the gate trench on the drift region and simultaneously forming a portion of the drift region other than the first region as a second region of a second impurity concentration smaller than the first impurity concentration by implanting a first conductivity type impurity from the front surface of the semiconductor layer after the formation of the gate trench.

20. The method for producing a semiconductor device according to claim 18, wherein

the step of forming the semiconductor layer includes a step of stacking the drift region, the body region and the source region in this order by epitaxy,

the step of growing the drift region includes a step of forming a second region of a second impurity concentration from the side of the rear surface of the semiconductor layer and forming a first region of a first impurity concentration greater than the second impurity concentration on the second region, and

the step of forming the gate trench includes a step of forming the gate trench so that the deepest portion of the gate trench reaches an intermediate portion in the thickness direction of the first region.

21. The method for producing a semiconductor device according to claim 18, further comprising:

a step, carried out simultaneously with the step of forming the gate trench, of forming a source trench having a sidewall and a bottom wall, passing through the source region and the body region from the front surface of the semiconductor layer and reaching the drift region; and

a step, carried out simultaneously with the step of implanting the impurity into the edge portion of the gate trench, of selectively implanting a second conductivity type impurity into an edge portion of the source trench where the sidewall and the bottom wall intersect with each other in a partial region of the source trench.

22. The method for producing a semiconductor device according to claim 18, wherein

the step of forming the semiconductor layer includes a step of forming the body region by performing ion implantation from the front surface of the semiconductor layer after forming the semiconductor layer by epitaxy.