Semiconductor Device and Method for Manufacturing a Semiconductor Device

• US 20130307059A1
• Filed: 05/21/2012
• Published: 11/21/2013
• Est. Priority Date: 05/21/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Weis, Rolf
• Granted Patent: US 9,685,511 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a first region of a first conductivity type and a body region of a second conductivity type, the first conductivity type being different from the second conductivity type. The body region is disposed on a side of a first surface of the semiconductor substrate. The semiconductor device further includes a plurality of trenches arranged in the first surface of the substrate, the trenches extending in a first direction having a component perpendicular to the first surface. Doped portions of the second conductivity type are adjacent to a lower portion of a sidewall of the trenches. The doped portions are electrically coupled to the body region via contact regions. The semiconductor device further includes a gate electrode disposed in an upper portion of the trenches.

Claims

15. A method of manufacturing a semiconductor device, the method comprising:

forming a plurality of trenches in a first surface of a semiconductor substrate, the semiconductor substrate comprising a first region of a first conductivity type and a body region of a second conductivity type, the first conductivity type being different from the second conductivity type, the trenches being formed so as to extend in a first direction having a component perpendicular to the first surface;

forming doped portions of the second conductivity type adjacent to a lower portion of a sidewall of the trenches;

electrically coupling the doped portions to the body region via contact regions; and

forming a gate electrode in an upper portion of the trenches.

1. A semiconductor device comprising:

a semiconductor substrate comprising a first region of a first conductivity type and a body region of a second conductivity type, the first conductivity type being different from the second conductivity type, the body region being disposed on a side of a first surface of the semiconductor substrate;

a plurality of trenches arranged in the first surface of the substrate, the trenches extending in a first direction having a component perpendicular to the first surface;

doped portions of the second conductivity type adjacent to a lower portion of a sidewall of the trenches, the doped portions being electrically coupled to the body region via contact regions; and

a gate electrode disposed in an upper portion of the trenches.

2. The semiconductor device of claim 1, wherein the first region includes a drift zone adjacent to the doped portions.

3. The semiconductor device of claim 1, wherein the doped portions of the second conductivity type line the sidewall and a bottom side of each of the trenches.

4. The semiconductor device of claim 1, wherein the semiconductor device is a vertical superjunction device including a charge compensation zone formed of the doped portions at opposing sidewalls of adjacent trenches and a part of a drift zone therebetween.

5. The semiconductor device of claim 1, wherein a portion of the trenches below the gate electrode is filled with an insulating material.

6. The semiconductor device of claim 1, wherein a channel region is disposed adjacent to the gate electrode, the channel region being electrically insulated from the gate electrode.

7. The semiconductor device of claim 1, wherein the trenches further extend in a second direction parallel to the first surface of the semiconductor substrate.

8. The semiconductor device of claim 1, wherein:

the contact regions are doped with impurities of the second conductivity type, the contact regions being electrically coupled to the body region; and

regions of the doped portions adjacent to a portion of a sidewall of the trenches are electrically coupled to the contact regions.

9. The semiconductor device of claim 8, wherein the contact regions extend in a third direction parallel to the first surface of the substrate, the third direction intersecting the second direction.

10. The semiconductor device of claim 1, wherein the contact regions are semiconductor regions buried in the semiconductor substrate and arranged between the body region and the doped regions.

11. The semiconductor device of claim 10, wherein an upper part of the contact regions overlap the body region and a lower part of the contact regions overlap the doped portions.

12. The semiconductor device of claim 1, wherein a channel region is disposed in the body region and adjoins the first region of the first conductivity type.

13. The semiconductor device of claim 1, wherein a lower side of the gate electrode is disposed over an upper side of the doped portions of the second conductivity type adjacent to the lower portion of the sidewall of the trenches.

14. An integrated circuit comprising the semiconductor device of claim 1.

16. The method of claim 15, wherein the trenches are formed to further extend in a second direction parallel to the first surface of the semiconductor substrate.

17. The method of claim 15, wherein forming the contact regions comprises forming regions doped with impurities of the second conductivity type so as to be electrically coupled to the body region, and forming the contact regions so as to be electrically coupled to regions of the doped portions adjacent to a portion of a sidewall of the trenches.

18. The method of claim 17, wherein the contact regions are formed so as to extend in a third direction parallel to the first surface of the substrate, the third direction intersecting the second direction.

19. The method of claim 18, wherein the contact regions are formed using a stripe mask extending in the third direction.

20. The method of claim 15, wherein forming the doped portions of the second conductivity type comprises lining the sidewall and a bottom side of each of the trenches with a material comprising dopants of the second conductivity type.

19-1. The method of claim 15, wherein the trenches are formed using a stripe mask extending in the second direction.

21. A superjunction semiconductor device including a charge compensation zone, the superjunction semiconductor device comprising:

a semiconductor substrate comprising a first surface and a second surface, a source region adjacent to the first surface, a drain region adjacent to the second surface;

trenches in the first surface of the semiconductor substrate;

a drift zone between the source region and the drain region;

a doped portion adjacent to a lower portion of the trenches, wherein the doped portion and a part of the drift zone adjoining the doped portion are part of the charge compensation zone; and

a gate electrode disposed in the trenches.

22. An integrated circuit comprising the superjunction semiconductor device of claim 21.