PACKAGING WITH INTERPOSER FRAME

• US 20130307140A1
• Filed: 05/18/2012
• Published: 11/21/2013
• Est. Priority Date: 05/18/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: HUANG, Hui-Min, LIN, Chih-Wei, CHENG, Ming-Da, LIU, Chung-Shi, CHEN, Chen-Shien, HU, Yen-Chang
• Granted Patent: US 9,991,190 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/495 Lead-frames or other flat leads H01L23/498 takes precedence; lead frame interconnections between components H01L23/52
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

The mechanisms of using an interposer frame to package a semiconductor die enables fan-out structures and reduces form factor for the packaged semiconductor die. The mechanisms involve using a molding compound to attach the semiconductor die to the interposer frame and forming a redistribution layer on one or both sides of the semiconductor die. The redistribution layer(s) in the package enables fan-out connections and formation of external connection structures. Conductive columns in the interposer frame assist in thermal management.

Claims

1. A semiconductor package, comprising:

an interposer frame, wherein the interposer frame includes a plurality of conductive columns;

a semiconductor die disposed in an opening within the interposer frame;

a molding compound between the interposer frame and the semiconductor die; and

a wiring layer, wherein the wiring layer connects with devices in the semiconductor die and the plurality of conductive columns of the interposer frame.

2. The semiconductor package of claim 1, wherein the wiring layer includes an insulating layer and a redistribution layer, wherein the redistribution layer extends beyond a boundary of the semiconductor die.

3. The semiconductor package of claim 1, wherein the plurality of conductive columns are isolated from each other with a molding compound.

4. The semiconductor package of claim 1, further comprising:

another wiring layer on an opposite side of the semiconductor die from the wiring layer, wherein the other wiring layer connects with the plurality of conductive columns of the interposer frame.

5. The semiconductor package of claim 1, wherein each of the plurality of conductive columns includes a main portion and an end portion attached to the main portion.

6. The semiconductor package of claim 1, wherein each of the plurality of conductive columns includes a curved surface.

7. The semiconductor package of claim 1, wherein each of the plurality of conductive columns includes copper or copper alloy.

8. The semiconductor package of claim 5, wherein the end portion is surrounded by the molding compound.

9. The semiconductor package of claim 5, wherein the end portion includes a stud bump and a wire.

10. The semiconductor package of claim 5, wherein the end portion is made of reflowed solder.

11. The semiconductor package of claim 1, wherein each of the plurality of conductive columns has a middle section wider than an end section thereof.

12. The semiconductor package of claim 1, wherein each of the plurality of conductive columns has substantially straight sidewalls or a middle section narrower than an end section thereof.

13. The semiconductor package of claim 1, wherein each of the plurality of the conductive columns has a height in a range from about 10 μ

m to about 600 μ

m.

14. The semiconductor package of claim 1, wherein each of the plurality of the conductive columns has a maximum width in a range from about 10 μ

m to about 600 μ

m.

15. A semiconductor package, comprising:

an interposer frame, wherein the interposer frame includes a plurality of conductive columns;

a semiconductor die disposed in an opening within the interposer frame;

a molding compound between the interposer frame and the semiconductor die;

a wiring layer, wherein the wiring layer connects with devices in the semiconductor die and the plurality of conductive columns of the interposer frame; and

another wiring layer on an opposite side of the semiconductor die from the wiring layer, wherein the other wiring layer connects with the plurality of conductive columns of the interposer frame.

16. A method of packaging a semiconductor die, the method comprising:

providing the semiconductor die;

providing an interposer frame, wherein the interposer frame has a plurality of conductive columns;

disposing the semiconductor die in an opening of the interposer frame;

forming a molding compound to fill space between the semiconductor die and the interposer frame;

removing a portion of the molding compound to expose the plurality of conductive columns; and

forming a redistribution layer to connect devices of the semiconductor die with the plurality of conductive columns.

17. The method of claim 16, wherein the redistribution layer extends beyond a boundary of the semiconductor die.

18. The method of claim 16, further comprising:

forming another redistribution layer on an opposite side of the semiconductor die from the redistribution layer, wherein the other redistribution layer connects with the plurality of conductive columns.

19. The method of claim 16, further comprising:

forming end portions attached to end sections of the plurality of conductive columns.

20. The method of claim 19, wherein forming the end portions further comprising:

forming openings connected to the end sections of the plurality of conductive columns;

plating a conductive material to fill the openings; and

removing excess conductive materials outside the openings.