STORAGE DEVICE AND WRITING METHOD OF THE SAME

• US 20130308372A1
• Filed: 05/13/2013
• Published: 11/21/2013
• Est. Priority Date: 05/17/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Shionoiri, Yutaka, Inoue, Seiko
• Granted Patent: US 8,929,128 B2
• Time in Patent Office: Days
• US Class Current: 365/149
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits

Abstract

A storage device in which held voltage is prevented from decreasing due to feedthrough in writing data to the storage device at high voltage is provided. The storage device includes a write circuit, a bit line, a word line, a transistor, and a capacitor. A gate of the transistor is electrically connected to the word line. One of a source and a drain of the transistor is electrically connected to the bit line. The other of the source and the drain of the transistor is electrically connected to one terminal of the capacitor. The other terminal of the capacitor is electrically connected to a ground. The write circuit includes an element holding write voltage and a circuit gradually decreasing voltage from the element holding write voltage. The write voltage is output from the write circuit to the word line.

Claims

1. A storage device comprising:

a memory cell comprising a first transistor; and

a write circuit,

wherein a gate of the first transistor is electrically connected to the write circuit through a word line,

wherein one of a source and a drain of the first transistor is electrically connected to a bit line,

wherein the write circuit is configured to set a potential of the word line to a first potential so that data is written to the memory cell, and

wherein the write circuit is configured to set the potential of the word line to a second potential by decreasing monotonically from the first potential to the second potential.

2. The storage device according to claim 1,

wherein the memory cell comprises a second capacitor,

wherein the other of the source and the drain of the first transistor is electrically connected to one electrode of the second capacitor, and

wherein the other electrode of the second capacitor is grounded.

3. The storage device according to claim 1,

wherein the memory cell comprises a second capacitor,

wherein the other of the source and the drain of the first transistor is electrically connected to one electrode of the second capacitor,

wherein the other electrode of the second capacitor is grounded, and

wherein electric charge is stored in the second capacitor when the data is written to the memory cell.

4. The storage device according to claim 1,

wherein the memory cell comprises a second transistor, and

wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor.

5. The storage device according to claim 1, wherein a channel formation region of the first transistor comprises an oxide semiconductor film.

6. The storage device according to claim 1,

wherein a channel formation region of the first transistor comprises an oxide semiconductor film, and

wherein the oxide semiconductor film comprises indium, gallium, zinc, and oxygen.

15. The storage device according to claim 1, wherein the potential of the word line is set to the second potential by decreasing gradually from the first potential to the second potential.

7. A storage device comprising:

a memory cell comprising a first transistor; and

a write circuit comprising a constant current circuit and a first capacitor,

wherein a gate of the first transistor is electrically connected to the constant current circuit and the first capacitor through a word line,

wherein one of a source and a drain of the first transistor is electrically connected to a bit line,

wherein the write circuit is configured to set a potential of the word line to a first potential so that data is written to the memory cell, and

wherein the write circuit is configured to set the potential of the word line to a second potential by decreasing monotonically from the first potential to the second potential when a current flows through the constant current circuit and electric charge stored in the first capacitor are discharged.

8. The storage device according to claim 7,

wherein the memory cell comprises a second capacitor,

wherein the other of the source and the drain of the first transistor is electrically connected to one electrode of the second capacitor, and

wherein the other electrode of the second capacitor is grounded.

9. The storage device according to claim 7,

wherein the memory cell comprises a second capacitor,

wherein the other of the source and the drain of the first transistor is electrically connected to one electrode of the second capacitor,

wherein the other electrode of the second capacitor is grounded, and

wherein electric charge is stored in the second capacitor when the data is written to the memory cell.

10. The storage device according to claim 7,

wherein the memory cell comprises a second transistor, and

wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor.

11. The storage device according to claim 7, wherein a channel formation region of the first transistor comprises an oxide semiconductor film.

12. The storage device according to claim 7,

wherein a channel formation region of the first transistor comprises an oxide semiconductor film, and

wherein the oxide semiconductor film comprises indium, gallium, zinc, and oxygen.

13. A driving method of a storage device comprising:

a memory cell comprising a first transistor; and

a write circuit,

wherein a gate of the first transistor is electrically connected to the write circuit through a word line, and

wherein one of a source and a drain of the first transistor is electrically connected to a bit line,

the driving method comprising the steps of;

setting a potential of the word line to a first potential so that data is written to the memory cell, and

setting the potential of the word line to a second potential by decreasing monotonically from the first potential to the second potential.

14. The driving method of a storage device according to claim 13,

wherein the memory cell comprises a second capacitor,

wherein the other of the source and the drain of the first transistor is electrically connected to one electrode of the second capacitor,

wherein the other electrode of the second capacitor is grounded, and

wherein electric charge is stored in the second capacitor when the data is written to the memory cell.

16. The storage device according to claim 13, wherein the potential of the word line is set to the second potential by decreasing gradually from the first potential to the second potential.

17. The driving method of a storage device according to claim 13, wherein the potential of the word line is set to the second potential by decreasing gradually from the first potential to the second potential.