CIRCUIT AND METHOD FOR CONTROLLING MRAM CELL BIAS VOLTAGES

• US 20130308374A1
• Filed: 05/10/2013
• Published: 11/21/2013
• Est. Priority Date: 05/17/2012
• Status: Active Grant

• Current Assignee: Everspin Technologies Incorporated
• Original Assignee: Everspin Technologies Incorporated
• Inventors: Gogl, Dietmar, Alam, Syed M., Andre, Thomas
• Granted Patent: US 9,183,912 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1697 Power supply circuits
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.

Claims

1. A method of controlling a plurality of biases applied to a plurality of memory devices, wherein a first terminal of each memory device is coupled to a bit line, a second terminal of each memory device is coupled to a first terminal of a select device, the select device having a control terminal coupled to a word line, and a second terminal of the select device coupled to a source line, the biases being applied to each of the memory devices by a bit line driver circuit coupled to the bit line, a source line driver circuit coupled to the source line, and a word line driver circuit coupled to the word line, the method comprising:

applying a first control bias to a control input of a replica bit line driver, the replica bit line driver having an output coupled to a replica bit line, wherein each replica memory device comprises a first terminal coupled to a replica bit line, a second terminal coupled to a first terminal of a replica select device, the select device having a control terminal coupled to a replica word line, and a second terminal coupled to a replica source line;

applying a second control bias to a control input of a replica source line driver, the replica source line driver having an output coupled to the source line driver circuit and a second terminal of the replica memory device;

applying a third control bias to a control input of a replica word line driver, the replica word line driver coupled to the word line driver circuit and a control terminal of a replica select device coupled to the replica memory device;

adjusting the magnitude of the first control bias in response to the voltage at the first terminal of the replica memory device; and

adjusting the magnitude of the second control bias in response to the voltage at the second terminal of the replica select device.

2. The method of claim 1 further comprising:

adjusting the magnitude of the third control bias in response to the voltage at one of the first or second terminals of the replica select device.

3. The method of claim 1, further comprising:

adjusting the magnitude of the third control bias in response to the voltage at the second terminal of the replica memory device.

4. The method of claim 1 wherein:

adjusting of the magnitude of the first control bias comprises regulating the voltage at the first terminal of the replica memory device to correlate with a first programmable voltage reference.

5. The method of claim 1 wherein:

adjusting of the magnitude of the second control bias comprises regulating the voltage at the second terminal of the replica select device to correlate to a second programmable voltage reference.

6. The method of claim 1, wherein:

adjusting the magnitude of the first control bias comprises regulating the voltage at the first terminal of the replica memory device to achieve a difference between the voltage at the first terminal of the replica memory device and the second terminal of the replica memory device that correlates to a third programmable voltage reference.

7. The method of claim 1, wherein:

adjusting the magnitude of the second control bias comprises regulating the voltage at the second terminal of the replica memory device to achieve a difference between the voltage at the first terminal of the memory device and the second terminal of the memory device that correlates to a fourth programmable voltage reference.

8. The method of claim 1 wherein:

adjusting the magnitude of the third control bias comprises regulating the replica word line voltage to achieve a difference between the replica word line voltage and a voltage on one of the first or second terminals of the replica select device that correlates to a fifth programmable voltage reference.

9. The method of claim 1 wherein:

the replica memory device comprises a resistive element with a resistance proportional to the resistance of the memory devices.

10. The memory of claim 1 wherein:

the first terminal of the replica memory device is coupled to the replica bit line driver by a resistive element.

11. The memory of claim 1 wherein:

the second terminal of the replica select device is coupled to the replica source line driver by a resistive element.

12. A memory comprising:

a memory array comprising;

a plurality of bit lines;

a plurality of source lines;

a plurality of word lines; and

a plurality memory cells arranged in a plurality of columns, each of the memory cells comprising;

a select device; and

a memory device coupled in series with the select device, each memory cell configured to be coupled to one of the word lines, and selectively coupled between one of the bit lines and one of the source lines;

a replica column comprising;

a replica bit line;

a replica source line;

a replica memory cell coupled between the replica bit line and the replica source line, the replica memory cell comprising;

a replica memory device; and

a replica select device coupled to the replica memory device and having a control electrode and at least one current carrying electrode;

at least one regulator circuit configured to;

regulate one of a source line voltage on a selected source line or a bit line voltage on a selected bit line;

regulate a word line voltage on a selected word line in response to a voltage across the control electrode and at least one current carrying electrode of the replica memory select device; and

regulate a memory device voltage across the memory device in response to a reference memory device voltage and a replica voltage across the replica memory device.

13. The memory of claim 12 wherein the at least one regulator circuit is further configured to:

regulate a source line voltage on a selected source line in response to both a reference source line voltage and a replica source line voltage on the replica source line.

14. The memory of claim 13 wherein the reference source line voltage is programmable.

15. The memory of claim 12 wherein the at least one regulator circuit is further configured to:

regulate a bit line voltage on a selected bit line in response to both a reference bit line voltage and a replica bit line voltage on the replica bit line.

16. The memory of claim 15 wherein the reference bit line voltage is programmable.

17. The memory of claim 12 wherein the at least one regulator circuit is further configured to:

regulate a word line voltage on a selected word line to maintain a reference control electrode to current carrying electrode voltage across the control electrode and at least one current carrying electrode of the replica memory select device.

18. The memory of claim 17 wherein the reference control electrode to current carrying electrode voltage is programmable

19. The memory of claim 12 wherein the memory comprises a first state having a first resistance range and a second state having a second resistance range, and the replica memory cell comprises at least one resistor having a resistance within the first or second range.

20. A method of providing bias voltages to a magnetic memory array including a plurality of columns of magnetic memory cells, each of the memory cells including a magnetic memory device coupled in series with a select device, each magnetic memory cell configured to be selectively coupled between a bit line and a source line, and each select device coupled to a word line, the method comprising:

when current is flowing through the magnetic memory cell in a first direction;

applying a source line voltage on the source line;

regulating a word line voltage on the word line to the sum of the source line voltage and a voltage across a gate and a source of the select device to correlate to a reference select device gate to source voltage; and

regulating a memory device voltage to correlate to a reference memory device voltage; and

when current is flowing through the magnetic memory cell in a second direction;

applying a bit line voltage on the bit line;

regulating a word line voltage on the word line to the sum of the source line voltage and a memory device voltage and a voltage across a gate and a source of the select device to correlate to a reference select device gate to source voltage; and

regulating a memory device voltage device to correlate to a reference memory device voltage.

21. The method of claim 20 further comprising:

regulating the source line voltage on the source line to correlate to a reference source line voltage.

22. The method of claim 20 further comprising:

regulating the bit line voltage on the bit line to correlate to a reference bit line voltage.

23. The method of claim 20 further comprising:

maintaining at least one of the bit line or the source line voltage at a fixed voltage level.