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CIRCUIT AND METHOD FOR CONTROLLING MRAM CELL BIAS VOLTAGES

  • US 20130308374A1
  • Filed: 05/10/2013
  • Published: 11/21/2013
  • Est. Priority Date: 05/17/2012
  • Status: Active Grant
First Claim
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1. A method of controlling a plurality of biases applied to a plurality of memory devices, wherein a first terminal of each memory device is coupled to a bit line, a second terminal of each memory device is coupled to a first terminal of a select device, the select device having a control terminal coupled to a word line, and a second terminal of the select device coupled to a source line, the biases being applied to each of the memory devices by a bit line driver circuit coupled to the bit line, a source line driver circuit coupled to the source line, and a word line driver circuit coupled to the word line, the method comprising:

  • applying a first control bias to a control input of a replica bit line driver, the replica bit line driver having an output coupled to a replica bit line, wherein each replica memory device comprises a first terminal coupled to a replica bit line, a second terminal coupled to a first terminal of a replica select device, the select device having a control terminal coupled to a replica word line, and a second terminal coupled to a replica source line;

    applying a second control bias to a control input of a replica source line driver, the replica source line driver having an output coupled to the source line driver circuit and a second terminal of the replica memory device;

    applying a third control bias to a control input of a replica word line driver, the replica word line driver coupled to the word line driver circuit and a control terminal of a replica select device coupled to the replica memory device;

    adjusting the magnitude of the first control bias in response to the voltage at the first terminal of the replica memory device; and

    adjusting the magnitude of the second control bias in response to the voltage at the second terminal of the replica select device.

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