MEMORY DEVICE AND METHOD FOR DRIVING MEMORY DEVICE

• US 20130308392A1
• Filed: 05/14/2013
• Published: 11/21/2013
• Est. Priority Date: 05/18/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Nishijima, Tatsuji, Miyake, Hiroyuki
• Granted Patent: US 8,953,358 B2
• Time in Patent Office: Days
• US Class Current: 365/189.02
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A memory device in which one memory cell can operate in both a single-level cell mode and a multi-level cell mode includes a signal transmission path for a multi-level cell mode in which a multi-bit digital signal representing any of three or more states input to the memory circuit is converted by a D/A converter and stored in the memory cell and the stored data is read by converting a signal output from the memory cell into a multi-bit digital signal with an A/D converter and the multi-bit digital signal is output from the memory circuit, and a signal transmission path for a single-level cell mode in which a single-bit digital signal representing any of two states input to the memory circuit is directly stored in the memory cell and the signal stored in the memory cell is directly output from the memory cell.

Claims

1. A memory device comprising:

a control circuit;

an input-output portion electrically connected to the control circuit;

an input signal line electrically connected to the input-output portion;

an output signal line electrically connected to the input-output portion;

a selection circuit electrically connected to the control circuit;

a selection signal line electrically connected to the selection circuit; and

a memory circuit electrically connected to the input signal line, the output signal line, and the selection signal line, the memory circuit comprising;

a memory cell;

a first switching element electrically connected between the input signal line and the memory cell;

a second switching element electrically connected between the output signal line and the memory cell;

a third switching element electrically connected to the input signal line;

a D/A converter electrically connected between the third switching element and the memory cell;

a fourth switching element electrically connected to the output signal line; and

an A/D converter electrically connected between the fourth switching element and the memory cell.

2. The memory device according to claim 1,

wherein the memory cell comprises:

a first transistor, one of a source and a drain of which is electrically connected to the first switching element and the D/A converter;

a capacitor, one of terminals of which is electrically connected to the other of the source and the drain of the first transistor;

a second transistor, a gate of which is electrically connected to the one of the terminals of the capacitor and the other of the source and the drain of the first transistor;

a signal supply portion electrically connected to one of the source and the drain of the second transistor and the other of the terminals of the capacitor; and

a third transistor, one of a source and a drain of which is electrically connected to the other of a source and a drain of the second transistor, and

wherein the other of the source and the drain of the third transistor is electrically connected to the second switching element and the A/D converter.

3. The memory device according to claim 2,

wherein an active layer of the first transistor includes an oxide semiconductor material.

4. An electronic device comprising the memory device according to claim 1.

5. A memory device comprising:

a memory circuit comprising a first signal transmission path for a single-level cell mode and a second signal transmission path for a multi-level cell mode;

a control circuit configured to select whether the memory circuit is used in the single-level cell mode or the multi-level cell mode;

an input-output portion configured to output a first signal based on the selection by the control circuit to the memory circuit and configured to be input a second signal from the memory circuit; and

a selection circuit configured to determine whether the first signal transmission path or the second signal transmission path is used based on the selection by the control circuit,

wherein the first signal transmission path includes a first input path including a first switching element, a first output path including a second switching element, and a memory cell electrically connected between the first input path and the first output path, and

wherein the second signal transmission path includes a second input path including a third switching element and a D/A converter, a second output path including a fourth switching element and an A/D converter, and the memory cell electrically connected between the second input path and the second output path.

6. The memory device according to claim 5,

wherein the memory cell includes a storage function portion configured to store the first signal and an output function portion configured to output the second signal.

7. The memory device according to claim 6,

wherein the storage function portion includes a first transistor, a second transistor, and a capacitor,

wherein the output function portion includes the second transistor and a signal supply portion,

wherein one of a source and a drain of the first transistor is electrically connected to the first input path and the second input path,

wherein the first signal input from the first input path is configured to be stored in a node which is electrically connected to the other of the source and the drain of the first transistor, a gate of the second transistor, and one of terminals of the capacitor,

wherein one of a source and a drain of the second transistor is electrically connected to the signal supply portion,

wherein the second signal based on the first signal is configured to be output from the other of the source and the drain of the second transistor, and

wherein an active layer of the first transistor includes an oxide semiconductor material.

8. The memory device according to claim 5, wherein the memory cell comprising:

a first transistor, one of a source and a drain of which is electrically connected to the first input path and the second input path;

a capacitor, one of terminals of which is electrically connected to the other of the source and the drain of the first transistor;

a second transistor, a gate of which is electrically connected to the one of the terminals of the capacitor and the other of the source and the drain of the first transistor;

a third transistor, one of a source and a drain of which is electrically connected to one of a source and a drain of the second transistor; and

a signal supply portion electrically connected to the other of the source and the drain of the second transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to the first output path and the second output path.

9. The memory device according to claim 8,

wherein an active layer of the first transistor includes an oxide semiconductor material.

10. The memory device according to claim 5, wherein the memory cell is configured to have properties of storing a written signal even when power is not supplied to the memory cell.

11. An electronic device comprising the memory device according to claim 5.

12. A method for driving a memory device including a memory circuit, the method comprising the steps of:

writing one of a single-bit data and a multi-bit data to a memory cell included in the memory circuit according to a selection by a control circuit electrically connected to the memory circuit; and

reading the one of the single-bit data and the multi-bit data from the memory cell,

wherein the memory circuit includes;

a first input path including a first switching element electrically connected to the memory cell;

a first output path including a second switching element electrically connected to the memory cell;

a second input path including a third switching element and a D/A converter electrically connected between the third switching element and the memory cell; and

a second output path including a fourth switching element and an A/D converter electrically connected between the fourth switching element and the memory cell,

wherein in the case of writing the single-bit data to the memory cell and reading the single-bit data from the memory cell, the single-bit data is written to the memory cell though the first input path and is read from the memory cell though the first output path, and

wherein in the case of writing the multi-bit data to the memory cell and reading the multi-bit data from the memory cell, the multi-bit data is written to the memory cell though the second input path and is read from the memory cell though the second output path.

13. The method according to claim 12,

wherein in the case of writing the single-bit data to the memory cell and reading the single-bit data from the memory cell, the third switching element and the fourth switching element are set in a non-conducting state and the first switching element and the second switching element are set in a conducting state, and

wherein in the case of writing the multi-bit data to the memory cell and reading the multi-bit data from the memory cell, the first switching element and the second switching element are set in a non-conducting state and the third switching element and the fourth switching element are set in a conducting state.

14. The method according to claim 12,

wherein the memory cell comprises:

a signal supply portion;

a first transistor, one of a source and a drain of which is electrically connected to the first input path and the second input path;

a second transistor, one of a source and a drain of which is electrically connected to the signal supply portion; and

a capacitor, one of terminals of which is electrically connected to the other of the source and the drain of the first transistor and a gate of the second transistor,

wherein a voltage of a signal supplied from the signal supply portion in the case of writing the single-bit data to the memory cell is lower than a voltage of a signal supplied from the signal supply portion in the case of writing the multi-bit data to the memory cell.

15. The method according to claim 14,

wherein an active layer of the first transistor includes an oxide semiconductor material.

16. A method for driving a memory device including a memory circuit, the method comprising the steps of:

writing a first multi-bit data to a memory cell included in the memory circuit, wherein the first multi-bit data includes a single-bit data and a second multi-bit data; and

reading one of the single-bit data and the second multi-bit data from the memory cell,

wherein the memory circuit further includes;

a first input path including a first switching element electrically connected to the memory cell;

a first output path including a second switching element electrically connected to the memory cell;

a second input path including a third switching element and a D/A converter electrically connected between the third switching element and the memory cell; and

a second output path including a fourth switching element and an A/D converter electrically connected between the fourth switching element and the memory cell,

wherein the first multi-bit data is written to the memory cell though the second input path,

wherein in the case of reading the single-bit data from the memory cell, the single-bit data is read from the memory cell though the first output path, and

wherein in the case of reading the second multi-bit data from the memory cell, the second multi-bit data is read from the memory cell though the second output path.

17. The method according to claim 16,

wherein the first multi-bit data includes the most significant bit, the second most significant bit, and bits lower than the second most significant bit,

wherein the single-bit data is set in the most significant bit of the first multi-bit data,

wherein the second most significant bit is set to 0, and

wherein the second multi-bit data is set in the bits.

18. The method according to claim 16,

wherein in the case of reading the single-bit data from the memory cell, the third switching element and the fourth switching element are set in a non-conducting state and the first switching element and the second switching element are set in a conducting state, and

wherein in the case of writing the first multi-bit data to the memory cell and reading the second multi-bit data from the memory cell, the first switching element and the second switching element are set in a non-conducting state and the third switching element and the fourth switching element are set in a conducting state.

19. The method according to claim 16,

wherein the memory cell comprises:

a signal supply portion;

a first transistor, one of a source and a drain of which is electrically connected to the first input path and the second input path;

a second transistor, one of a source and a drain of which is electrically connected to the signal supply portion; and

a capacitor, one of terminals of which is electrically connected to the other of the source and the drain of the first transistor and a gate of the second transistor.

20. The method according to claim 19,

wherein an active layer of the first transistor includes an oxide semiconductor material.