READ SELF TIMING CIRCUITRY FOR SELF-TIMED MEMORY

• US 20130308397A1
• Filed: 05/18/2012
• Published: 11/21/2013
• Est. Priority Date: 05/18/2012
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Pvt Ltd. (STMicroelectronics NV)
• Inventors: Kohli, Nishu
• Granted Patent: US 8,854,901 B2
• Time in Patent Office: Days
• US Class Current: 365/189.15
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits

Abstract

A self-timed memory includes a plurality of timer cells each including an access transistor coupled to a true node and having a gate coupled to a reference wordline actuated by a reference wordline driver. Self-timing is effectuated by detecting completion of reference true bitline discharge in the timer cells resulting in enabling a sense amplifier. To better align detected completion of the discharge by the timer cells to a read from actual memory cells at any voltage in the operating voltage range of the memory, the gate to source voltage of the timer cells'"'"' access transistors is lowered by decreasing the logic high voltage level applied by the reference wordline. The timer cells may also, or alternatively, have pulldown transistors coupled to the internal true node, wherein a gate terminal of the pulldown is coupled to the reference wordline node and activated with the lowered gate to source voltage.

Claims

1. A circuit, comprising:

a memory cell array including;

a first section having a plurality of memory cells and a wordline for each row of memory cells in said first section; and

a second section having a plurality of read timer cells arranged in a column, each read timer cell including a reference wordline, a reference true bitline, an internal true node, an access transistor coupled between said internal true node and said reference true bitline and a pull-down transistor coupled between said internal true node and a reference supply node, wherein the reference true bitline is shared by the column of read timer cells;

a reference row decoder circuit coupled to the second section of the memory cell array, said reference row decoder circuit including a reference wordline driver circuit having an output coupled to drive the reference wordline; and

means for lowering a gate to source voltage of timer cell transistors by decreasing a higher voltage level corresponding to logic high that is applied on said reference wordline to actuate said at least one of said access transistor and pull-down transistor during a read operation of memory cells in the first section.

2. The circuit of claim 1, wherein the decreased voltage level is equal to a high supply voltage for the cell array minus a delta voltage value.

3. The circuit of claim 2, wherein the delta voltage value is equal to an estimated shift in threshold voltage of at least one transistor in a memory cell with a statistically worst read current among the plurality of memory cells in the first section of the memory cell array.

4. The circuit of claim 1, wherein the reference wordline driver circuit includes a buffer circuit and the means for lowering comprises a voltage lowering circuit coupled between a high supply voltage node and a higher supply node of said buffer circuit, said voltage lowering circuit operable to apply an intermediate supply voltage to said higher supply node which is equal to a high supply voltage minus a delta voltage value.

5. The circuit of claim 4, wherein the delta voltage value is equal to an estimated shift in threshold voltage of at least one transistor in a memory cell with a statistically worst read current among the plurality of memory cells in the first section of the memory cell array.

6. The circuit of claim 1, wherein the means for lowering comprises a voltage restricting circuit coupled to the reference wordline and configured to limit a logic high voltage applied by the reference wordline driver circuit to said reference wordline to a value which is equal to a high supply voltage minus a delta voltage value.

7. The circuit of claim 6, wherein the delta voltage value is equal to an estimated shift in threshold voltage of at least one transistor in a memory cell with a statistically worst read current among the plurality of memory cells in the first section of the memory cell array.

8. The circuit of claim 1, wherein the means for lowering comprises a pull-down circuit coupled to the reference wordline and configured to control voltage drop on the reference wordline to be same as an equivalent estimated shift in threshold voltage of at least one transistor in a memory cell with a statistically worst read current among the plurality of memory cells in the first section of the memory cell array.

9. The circuit of claim 8, wherein the pull-down circuit comprises a pull-down resistance coupled between the reference wordline and a ground supply node.

10. The circuit of claim 1, further comprising a detection circuit coupled to said reference true bitline and having an output whose logic state changes in response to completion of discharge of the reference true bitline by said timer cells during the read operation.

11. Self-timing circuitry for use in a memory, said memory including a plurality of memory cells, comprising:

a plurality of timer cells arranged in a column;

a reference true bitline coupled to the column of write timer cells;

a reference wordline for each timer cell in the column;

wherein each timer cell includes an internal true node, an access transistor coupled between said internal true node and said reference true bitline and a pull-down transistor coupled between said internal true node and a reference supply node;

a reference wordline driver circuit having an output coupled to said reference wordline;

a detection circuit coupled to said reference true bitline and having an output whose logic state changes in response to completion of discharge of the reference true bitline during a read operation; and

a circuit configured to lower a gate to source voltage of timer cell transistors by decreasing a higher voltage level corresponding to logic high, the decreased voltage for application on said reference wordline to actuate at least one of said access transistor and pull-down transistor during a read operation of memory cells in the memory.

12. The circuitry of claim 11, wherein the decreased voltage level is equal to a high supply voltage for the memory minus a delta voltage value.

13. The circuitry of claim 12, wherein the delta voltage value is equal to an estimated shift in threshold voltage of at least one transistor in a memory cell with a statistically worst read current among the plurality of memory cells in the memory.

14. The circuitry of claim 11, wherein the reference wordline driver circuit includes a buffer circuit and the circuit configured to lower comprises a voltage lowering circuit coupled between a high supply voltage node and a higher supply node of said buffer circuit, said voltage lowering circuit operable to apply an intermediate supply voltage to said higher supply node which is equal to a high supply voltage minus a delta voltage value.

15. The circuitry of claim 11, wherein said circuit configured to lower comprises a voltage restricting circuit coupled to the reference wordline and configured to limit a logic high voltage applied by the reference wordline driver circuit to said reference wordline to a value which is equal to a high supply voltage minus a delta voltage value.

16. The circuitry of claim 11, wherein said circuit configured to lower comprises a pull-down circuit coupled to the reference wordline and configured to control voltage drop on the reference wordline to be same as an equivalent estimated shift in threshold voltage of at least one transistor in a memory cell with a statistically worst read current among the plurality of memory cells in the memory.

17. The circuitry of claim 16, wherein the pull-down circuit comprises a pull down resistance coupled between the reference wordline and a ground supply node.

18. A method, comprising:

reading a logic value from a true side of a timer cell of a self-timed memory, said timer cell including an access transistor coupled between an internal true node and a reference true bitline and a pull-down transistor coupled between said internal true node and a reference supply node;

detecting a completion of a discharge of the reference true bitline by the read timer cell of the self-timed memory;

signaling an enabling of a sense amplifier operation of the self-timed memory in response to detected discharge completion; and

lowering a gate to source voltage of a read timer cell transistor by decreasing a higher voltage level corresponding to logic high, the decreased voltage for application on said reference wordline to actuate at least one of said access transistor and pull-down transistor during said logic value read.

19. The method of claim 18, wherein lowering adjusts a timing of discharge of the reference true bitline by the timer cell to better match a timing of discharge of a bitline for a memory cell in the self-timed memory beyond a sense amplifier offset for a sense amplifier coupled to that memory cell.

20. The method of claim 18, wherein lowering adjusts a timing of discharge of a reference bitline for the timer cell resulting in a better match with timing for generation of a voltage differential by a statistically worst read current generating memory cell at sense amplifier inputs sufficient for successful sense amplifier resolution throughout an operating voltage range of the self-timed memory.

21. The method of claim 18, wherein a decreased higher voltage level is equal to a high supply voltage for the memory minus a delta voltage value.

22. The method of claim 21, wherein the delta voltage value is equal to an estimated shift in threshold voltage of at least one transistor in a memory cell with a statistically worst read current among the plurality of memory cells in the memory.

23. The method of claim 18, wherein lowering comprises lowering a higher supply voltage for a reference wordline driver circuit that is operable to perform the step of discharging the reference true bitline.

24. The method of claim 19, wherein lowering comprises restricting a higher voltage applied on the reference wordline to a value less than a high supply voltage in connection with actuating at least one of said access transistor and pull-down transistor in the timer cell.

25. The method of claim 19, wherein lowering comprises resistively pulling down on the reference wordline to a value less than a high supply voltage when actuated to read from the timer cell.