WRITE SELF TIMING CIRCUITRY FOR SELF-TIMED MEMORY
First Claim
1. A circuit, comprising:
- a memory cell array including;
a first section having a plurality of memory cells and at least one data bit line for each column of memory cells in said first section; and
a second section having a plurality of write timer cells arranged in a column, each write timer cell including an internal true node, an internal complement node and a pullup transistor having a gate terminal coupled to said internal true node, said second section including at least one reference bit line coupled to the column of write timer cells and having a true reference internal line coupled to the internal true nodes of the column of write timer cells;
column circuitry coupled to the first and second sections of the memory cell array, said column circuitry including a reference write driver circuit having an output coupled to drive said at least one reference bit line; and
means for lowering a gate to source voltage of the write timer cell pullup transistor by raising a lower voltage level to which said internal true node is pulled down during a write operation to a voltage level above logic low level.
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Accused Products
Abstract
A self-timed memory includes a plurality of write timer cells. A reference write driver circuit writes a logic low value to a true side of the write timer cells. Each write timer cell includes a pullup transistor whose gate is coupled to an internal true node. Self-timing is effectuated by detecting a completion of the logic value write at a complement side of the write timer cells and signaling a reset of the self-timer memory in response to detected completion. To better align detected completion of the write in write timer cells to actual completion of a write in the memory, a gate to source voltage of the write timer cell pullup transistor is lowered by increasing a lower logic level voltage at the internal true node in connection with driver circuit operation to write a low logic state into the true side of the write timer cell.
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Citations
30 Claims
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1. A circuit, comprising:
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a memory cell array including; a first section having a plurality of memory cells and at least one data bit line for each column of memory cells in said first section; and a second section having a plurality of write timer cells arranged in a column, each write timer cell including an internal true node, an internal complement node and a pullup transistor having a gate terminal coupled to said internal true node, said second section including at least one reference bit line coupled to the column of write timer cells and having a true reference internal line coupled to the internal true nodes of the column of write timer cells; column circuitry coupled to the first and second sections of the memory cell array, said column circuitry including a reference write driver circuit having an output coupled to drive said at least one reference bit line; and means for lowering a gate to source voltage of the write timer cell pullup transistor by raising a lower voltage level to which said internal true node is pulled down during a write operation to a voltage level above logic low level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. Self-timing circuitry for use in a memory, said memory including a plurality of memory cells, comprising:
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a plurality of write timer cells arranged in a column, each write timer cell including a reference word line shared in common with said write timer cells, an internal true node, an internal complement node and a pullup transistor having a gate terminal coupled to said internal true node; a reference bit line coupled to the column of write timer cells; a complement reference internal line coupled to the internal complement nodes of the column of write timer cells; a reference write driver circuit having an output coupled to said reference bit line and configured to initiate a write operation in said write timer cells; a detecting circuit coupled to said complement reference internal line and having an output whose logic state changes in response to completion of said write operation in said write timer cells; and a circuit configured to lower a gate to source voltage of the write timer cell pullup transistors by raising a lower logic level voltage to which said internal true nodes are pulled down during a write operation to a voltage level above logic low level. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23)
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24. A method, comprising:
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writing a first logic value to a true side of a write timer cell of a self-timed memory, said write timer cell including a pullup transistor having a gate terminal coupled to an internal true node; detecting a completion of a second logic value write at a complement side of the write timer cell of the self-timed memory; signaling a write reset of the self-timer memory in response to detected completion; and lowering a gate to source voltage of the write timer cell pullup transistor by raising a lower logic level voltage to which said internal true node is pulled down during a write operation to a voltage level above logic low level. - View Dependent Claims (25, 26, 27, 28, 29, 30)
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Specification