METHOD FOR MANUFACTURING TRANSISTOR

• US 20130309808A1
• Filed: 06/10/2011
• Published: 11/21/2013
• Est. Priority Date: 12/01/2010
• Status: Active Grant

• Current Assignee: Peking University Shenzhen Graduate School
• Original Assignee: Peking University Shenzhen Graduate School
• Inventors: Zhang, Shengdong, He, Xin, Wang, Longyan
• Granted Patent: US 9,129,992 B2
• Time in Patent Office: Days
• US Class Current: 438/104
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Designs and fabrication of dual-gate thin film transistors are provided. An active region and a top gate electrode of the transistor can be made of a transparent thin film material. A photoresist can be coated onto a surface of the transparent conductive thin film for forming the top gate electrode. Light is from the bottom of the substrate during exposure. After the development, a photoresist pattern aligned with the bottom gate electrode is formed on the surface of the conductive thin film. The top gate electrode aligned with the bottom gate electrode is formed by etching the conductive thin film. The bottom gate electrode can be used as a mask, which may save the cost for manufacturing the transistor and improve the accuracy of alignment between the top gate electrode and the bottom gate electrode and the performance of the dual-gate thin film transistor.

Claims

1. A method for manufacturing a transistor, comprising

forming a bottom gate electrode, an active region and a conductive thin film on a top of a substrate, orderly;

coating a photoresist on the conductive thin film and forming a photoresist pattern by exposure during which light is from a bottom of the substrate; and

etching the conductive thin film to form a top gate electrode by using the photoresist pattern formed by photolithography.

2. The method according to claim 1, wherein the bottom gate electrode is made of a non-transparent material.

3. The method according to claim 2, wherein a bottom gate dielectric layer is formed between the bottom gate electrode and the active region, a top gate dielectric is formed between the active region and the conductive thin film, the conductive thin film and the top gate dielectric are simultaneously etched by using the photoresist pattern formed by photolithography as a mask to form the top gate electrode and the top gate dielectric layer, respectively, and the substrate, the bottom gate dielectric layer, the active region, the top gate dielectric and the conductive thin film are transparent.

4. The method according to claim 3, wherein the step of forming a bottom gate electrode, an active region and a conductive thin film on a top of a substrate, orderly, comprises:

forming a metal thin film on the top of the substrate and then photolithographing and etching the metal thin film to form the bottom gate electrode;

forming a bottom gate dielectric layer on the substrate and the bottom gate electrode;

forming a metal oxide semiconductor layer for forming the active region on the bottom gate dielectric layer, forming an active region-protecting thin film, and then simultaneously photolithographing and etching the metal oxide semiconductor layer and the active region-protecting thin film so as to form the active region and a protective layer covering a top surface of the active region, respectively, wherein a portion of the active region aligned with the bottom gate electrode and the top gate electrode is a channel region, and two portions of the active region beside the channel region are a source region and a drain region;

forming the top gate dielectric on the protective layer so as to cover the active region and the protective layer with the top gate dielectric and to extend the top gate dielectric onto the bottom gate dielectric layer; and

forming the conductive thin film for forming the top gate electrode on the top gate dielectric.

5. The method according to claim 4, wherein a material of the protective layer is same to or different from that of the top gate dielectric layer.

6. The method according to claim 1, further comprising processing the source region and the drain region by plasma projection after the top gate electrode is formed.

7. The method according to claim 6, wherein the plasma projection is argon plasma projection, hydrogen plasma projection or ammonia plasma projection.

8. The method according to claim 7, wherein the power of the plasma projection is 100-200 W and the pressure of the plasma projection is 0.1-1 Torr where the plasma projection is argon plasma projection.

9. The method according to claim 1, wherein the bottom gate electrode is made of Cr, Mo, Ti or Al and has a thickness of 100-300 nm, the top gate electrode is made of indium tin oxide or aluminum zinc oxide and has a thickness of 100-300 nm, and the active region is made of a material based on zinc oxide or indium oxide and has a thickness of 50-200 nm.

10. The method according to claim 2, wherein each of the bottom gate dielectric layer and the top gate dielectric layer is made of silicon nitride or silicon oxide, has a thickness of 100-400 nm, and formed by PECVD or magnetron sputtering, or each of the bottom gate dielectric layer and the top gate dielectric layer is made of aluminum oxide, tantalum oxide or hafnium oxide, has a thickness of 100-400 nm, and formed by magnetron sputtering.