THIN FILM TRANSISTOR ARRAY SUBSTRATE FOR A DISPLAY PANEL AND A METHOD FOR MANUFACTURING A THIN FILM TRANSISTOR ARRAY SUBSTRATE FOR A DISPLAY PANEL

• US 20130309821A1
• Filed: 04/25/2013
• Published: 11/21/2013
• Est. Priority Date: 06/03/2009
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: YOO, Hyeong-Suk, LEE, Ho-Jun, KIM, Sung-Ryul, SEO, O-Sung, CHIN, Hong-Kee
• Granted Patent: US 8,652,886 B2
• Time in Patent Office: Days
• US Class Current: 438/158
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

A method of manufacturing a thin film transistor array substrate includes forming a gate pattern on a substrate, forming a gate insulating film on the substrate, forming a source/drain pattern and a semiconductor pattern on the substrate, forming first, second, and third passivation films successively on the substrate. Over the above multi-layered passivation film forming a first photoresist pattern including a first portion formed on part of the drain electrode and on the pixel region, and a second portion. The second portion is thicker than the first portion. Then, patterning the third passivation film using the first photoresist pattern, forming a second photoresist pattern by removing the first portion of the first photoresist pattern, forming a transparent electrode film on the substrate, removing the second photoresist pattern and the transparent electrode film disposed on the second photoresist pattern, and forming a transparent electrode pattern on the second passivation layer.

Claims

1. A method for manufacturing a thin film transistor array substrate for a display panel comprises:

forming a gate pattern on a substrate, wherein the gate pattern includes a gate electrode, a plurality of gate lines and a plurality of storage electrode lines;

forming a gate insulating film on the gate pattern including the gate electrode, the plurality of gate lines and the plurality of storage electrode lines;

forming a source/drain pattern and a semiconductor pattern on the substrate, wherein the source/drain patterns includes a plurality of data lines, a source electrode and a drain electrode;

forming a first passivation film, a second passivation film, and a third passivation film successively on the substrate;

forming the first photoresist pattern which includes a first portion formed on part of the drain electrode and on a pixel region and a second portion formed on the semiconductor pattern which includes a channel region between the source electrode and the drain electrode, and wherein the second portion of the photoresist pattern has a relatively higher height than the first portion;

patterning an exposed portion of the first passivation film, the second passivation film and the third passivation film using the first photoresist pattern;

forming the second photoresist pattern by removing the first portion of the first photoresist pattern using an etch-back process;

patterning an exposed portion of the third passivation layer around the pixel region using the second photoresist pattern, wherein the patterning of the third passivation film includes over-etching the third passivation film;

forming a transparent electrode film on the substrate;

removing the second photoresist pattern and the transparent electrode film disposed on the second photoresist pattern; and

forming a transparent electrode pattern on the second passivation layer.

2. The method of claim 1, wherein the transparent electrode pattern includes a pixel electrode, an upper gate pad electrode and upper data pad electrode.

3. The method of claim 2, wherein the pixel electrode is formed having a plane shape and wherein the plane shape of the pixel electrode is substantially the same as a plane shape in an open region of the second photoresist pattern.

4. The method of claim 1, wherein the over-etching of the third passivation layer is performed using an etching gas including a mixture of sulfur hexa fluoride (SF₆) and oxygen (O₂).

5. The method of claim 4, wherein the third passivation layer has a high etch rate compared to the first passivation layer under the same etch conditions.

6. The method of claim 5, wherein the third passivation layer has an etch selectivity value over about 2:

1 compared to the first passivation layer.

7. The method of claim 1, wherein the transparent electrode film is made of one of indium-tin-oxide (ITO), a tin-oxide (TO) and an indium-zinc-oxide (IZO).