AMPLIFIER AND MOBILE COMMUNICATION DEVICE

• US 20130310114A1
• Filed: 05/16/2012
• Published: 11/21/2013
• Est. Priority Date: 05/16/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Friedrich-Alexander-Universitat Erlangen-Nurnberg, Intel Mobile Communications GmbH (Intel Corporation)
• Inventors: Leuschner, Stephan, Mueller, Jan-Erik, Zohny, Amr
• Granted Patent: US 9,088,248 B2
• Time in Patent Office: Days
• US Class Current: 455/571
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence

Abstract

An amplifier includes a first lower active sub cell and a second lower active sub cell, each comprising an input terminal and an output terminal, wherein the input terminals of the lower active sub cells are connected to the amplifier input and the output terminals of the lower active sub cells are not shorted. Furthermore, the amplifier includes a first upper active sub cell and a second upper active sub cell, each including a biasing terminal, wherein the input terminals and the output terminals of the upper active sub cells are coupled between the output terminals of the lower active sub cells and the amplifier output. The amplifier includes a bias controller configured to provide a first biasing signal to the first upper active sub cell and a second biasing signal to the second upper active sub cell based on an output power of the output signal.

Claims

1. An amplifier comprising:

an amplifier input for receiving an input signal;

an amplifier output for providing an output signal;

a first lower active sub cell and a second lower active sub cell, each comprising an input terminal and an output terminal, wherein the input terminals of the lower active sub cells are connected to the amplifier input and the output terminals of the lower active sub cells are not shorted;

a first upper active sub cell and a second upper active sub cell, each comprising a biasing terminal, an input terminal and an output terminal, wherein the input terminals and the output terminals of the upper active sub cells are coupled between the output terminals of the lower active sub cells and the amplifier output; and

a bias controller configured to provide a first biasing signal to the biasing terminal of the first upper active sub cell and a second biasing signal to the biasing terminal of the second upper active sub cell in dependence on an output power of the output signal.

2. The amplifier according to claim 1, wherein the upper active sub cells are configured such that a potential at their input terminals is dependent on a potential at their biasing terminals.

3. The amplifier according to claim 1, wherein the bias controller is configured to adjust a potential at the input terminal of the first upper active sub cell by means of the first biasing signal and to adjust a potential at the input terminal of the second upper active sub cell by means of the second biasing signal.

4. The amplifier according to claim 1, wherein the bias controller comprises a plurality of different bias sets, each bias set comprising a potential value for the first biasing signal and a potential value for the second biasing signal, wherein the bias controller is configured to choose for a given output power of the output signal the bias set out of the plurality of bias sets having the highest linearity for the given output power out of the plurality of bias sets.

5. The amplifier according to claim 4, wherein at least for some of the bias sets of the plurality of bias sets a potential value for the first biasing signal is different from a potential value for the second biasing signal.

6. The amplifier according to claim 1, further comprising a coupling impedance which is connected between the output terminals of the lower active sub cells.

7. The amplifier according to claim 1, further comprising a coupling filter which is connected between the output terminals of the lower active sub cells.

8. The amplifier according to claim 7, wherein the coupling filter is chosen such that that a cross modulation between the output terminals of the lower active sub cells reduces third order intermodulation products when compared to a case in which the output terminals of the lower active sub cells are shorted.

9. The amplifier according to claim 1,

wherein the input terminal of the first upper active sub cell is connected to the output terminal of the first lower active sub cell;

and

wherein the input terminal of the second upper active sub cell is connected to the output terminal of the second lower active sub cell.

10. The amplifier according to claim 1, wherein the output terminal of the first upper active sub cell is connected to the output terminal of the second upper active sub cell.

11. The amplifier according to claim 10, further comprising a further active sub cell comprising an input terminal and an output terminal, wherein the input terminal of the further active sub cell is connected to the output terminals of the upper active sub cells and wherein the output terminal of the further active sub cell is connected to the amplifier output.

12. The amplifier according to claim 11, wherein the further sub cell comprises a biasing terminal and wherein the bias controller is configured to provide a further biasing signal to the biasing terminal of the further active sub cell in dependence of the output power of the output signal.

13. The amplifier according to claim 11, wherein the further active sub cell comprises a transistor, a control terminal of which is connected to a shunt capacitance, and a switchable path of which is coupled between the input terminal and the output terminal of the further active sub cell.

14. The amplifier according to claim 11,

wherein the further active sub cell comprises a cascode comprising a lower transistor and an upper transistor, wherein switchable paths of the lower transistor and the upper transistor are coupled between the input terminal and the output terminal of the further sub cell;

and

wherein the bias controller is configured to provide a first additional biasing signal to a control terminal of the lower transistor and a second additional biasing signal to a control terminal of the upper transistor in dependence on the output power of the output signal.

15. The amplifier according to claim 1,

wherein the first upper active sub cell comprises a first transistor, a control terminal of which is connected to the biasing terminal of the first upper active sub cell and a switchable path of which is coupled between the input terminal and the output terminal of the first upper active sub cell;

and

wherein the second upper active sub cell comprises a first transistor, a control terminal of which is connected to the biasing terminal of the second upper active sub cell and a switchable path of which is coupled between the input terminal and the output terminal of the second upper active sub cell.

16. The amplifier according to claim 15, where a gate width of the first transistor of the first upper active sub cell is different from a gate width of the first transistor of the second upper active sub cell.

17. The amplifier according to claim 1,

wherein the first lower active sub cell comprises a first transistor, a control terminal of which is connected to the amplifier input and a switchable path of which is coupled between a reference potential terminal of the amplifier and the output terminal of the first lower active sub cell;

and

wherein the second lower active sub cell comprises a second transistor, a control terminal of which is connected to the amplifier input and a switchable path of which is coupled between the reference potential terminal and the output terminal of the second lower active sub cell.

18. The amplifier according to claim 1, wherein transistors of the active sub cells are from the same type of transistors out of NPN, PNP, P-MOS, N-MOS.

19. The amplifier according to claim 1, wherein the first lower active sub cell and the first active sub cell are chosen to amplify the input signal, while the second lower active sub cell and the second upper active sub cell are chosen for adjusting a linearity of the amplifier by means of the second biasing signal in dependence on the output power of the output signal.

20. The amplifier according to claim 1,

wherein the amplifier is configured to amplify a differential input signal comprising the input signal and a further input signal and to provide a differential output signal comprising the output signal and a further output signal;

wherein the amplifier further comprises;

a further input for receiving the further input signal and a further output for providing the further output signal;

a third lower active sub cell and a fourth lower active sub cell, each comprising an input terminal and an output terminal, wherein the input terminals of the third lower active sub cell and the fourth lower active sub cell are connected to the further amplifier input and the output terminals of the third lower active sub cell and the fourth lower active sub cell are not shorted; and

a third upper active sub cell and a fourth upper active sub cell, each comprising a biasing terminal, an input terminal and an output terminal, wherein the input terminals and the output terminals of the third upper active sub cell and the fourth upper active sub cell are coupled between the output terminals of the third lower active sub cell and the fourth lower active sub cell and the further amplifier output; and

wherein the bias controller is configured to provide a third biasing signal to the biasing terminal of the third upper active sub cell and a fourth biasing signal to the biasing terminal of the fourth upper active sub cell in dependence on the output power of the output signal.

21. The amplifier according to claim 20,

further comprising a first coupling impedance or coupling filter which is connected between the input terminal of the first upper active sub cell and the input terminal of the fourth upper active sub cell;

and

a second coupling impedance or coupling filter which is connected between the input terminal of the second upper active sub cell and the input terminal of the third upper active sub cell.

22. The amplifier according to claim 20, wherein the bias controller is configured to provide the first biasing signal and the third biasing signal such that they are for every output power of the output signal equal and to provide the second and the fourth biasing signal such that they are for every output power of the output signal equal.

23. An amplifier comprising:

an amplifier input for receiving an input signal;

an amplifier output for providing an output signal;

a first lower transistor and a second lower transistor, each comprising a control terminal, a first terminal and a second terminal, wherein the control terminals of the lower transistors are connected to the amplifier input, the second terminals of the lower transistors are not shorted and the first terminals of the lower transistor are coupled to a reference potential terminal of the amplifier;

a first upper transistor and a second upper transistor, each comprising a control terminal, a first terminal and a second terminal, wherein the first terminal of the first upper transistor is connected to the second terminal of the first lower transistor, the first terminal of the second upper transistor is connected to the second terminal of the second lower transistor and the second terminals of the upper transistors are shorted;

a cascode comprising a lower cascode transistor and an upper cascode transistor, wherein a first terminal of the lower cascode transistor is connected to the second terminals of the upper transistors and a second terminal of the upper cascode transistor is connected to the amplifier output; and

a bias controller configured to provide a first biasing signal to the biasing terminal of the first upper active sub cell, a second biasing signal to the biasing terminal of the second upper active sub cell, a third biasing signal to a control terminal of the lower cascode transistor and a fourth biasing signal to a control terminal of the upper cascode transistor in dependence on an output power of the output signal.

24. A mobile communication device comprising:

a baseband processor configured to provide a baseband signal;

an RF modulator configured to provide, based on the baseband signal an input signal;

an amplifier comprising;

an amplifier input for receiving the input signal;

an amplifier output for providing an output signal;

a first lower active sub cell and a second lower active sub cell, each comprising an input terminal and an output terminal, wherein the input terminals of the lower active sub cells are connected to the amplifier input and the output terminals of the lower active sub cells are not shorted;

a first upper active sub cell and a second upper active sub cell, each comprising a biasing terminal, an input terminal and an output terminal, wherein the input terminals and the output terminals of the upper active sub cells are coupled between the output terminals of the lower active sub cells and the amplifier output;

a bias controller configured to provide a first biasing signal to the biasing terminal of the first upper active sub cell and a second biasing signal to the biasing terminal of the second upper active sub cell in dependence on an output power of the output signal; and

an antenna configured to receive the output signal and to relay the output signal.