OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME

• US 20130313548A1
• Filed: 04/15/2013
• Published: 11/28/2013
• Est. Priority Date: 12/25/2007
• Status: Active Grant

• Current Assignee: Idemitsu Kosan Company Limited
• Original Assignee: Idemitsu Kosan Company Limited
• Inventors: YANO, Koki, KAWASHIMA, Hirokazu, INOUE, Kazuyoshi, TOMAI, Shigekazu, KASAMI, Masashi
• Granted Patent: US 8,791,457 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: C23C 14/086 of zinc, germanium, cadmium, indium, tin, thallium or bismuth
• CPC Class Codes: H01L 29/263 Amorphous materials
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A field effect transistor including a semiconductor layer including a composite oxide which contains In, Zn, and one or more elements X selected from the group consisting of Zr, Hf, Ge, Si, Ti, Mn, W, Mo, V, Cu, Ni, Co, Fe, Cr, Nb, Al, B, Sc, Y and lanthanoids in the following atomic ratios (1) to (3):

In/(In+Zn)=0.2 to 0.8  (1)

In/(In+X)=0.29 to 0.99  (2)

Zn/(X+Zn)=0.29 to 0.99  (3).

Claims

1. (canceled)

2. A field effect transistor comprising a semiconductor layer, the semiconductor layer comprising a composite oxide comprising In and Zn in an atomic ratio of In/(In+Zn) of 0.2 to 0.8, wherein

a radical distribution function (RDF) obtained by grazing incidence X-ray scattering of the semiconductor layer satisfies the relationship

A/B>

0.7

where A is the maximum value of RDF with an interatomic distance of 0.30 to 0.36 nm and B is the maximum value of RDF with an interatomic distance of 0.36 to 0.42.

3. The field effect transistor according to claim 2, wherein the In/(In+Zn) of 0.2 to 0.75.

4. The field effect transistor according to claim 2, wherein the relationship A/B>

0.85 is satisfied.

5. The field effect transistor according to claim 2, wherein the relationship A/B>

1 is satisfied.

6. The field effect transistor according to claim 2, wherein the relationship A/B>

1.2 is satisfied.

7. The field effect transistor according to claim 2, wherein the average In—

In bonding distance of the semiconductor layer is 0.3 to 0.322 nm.

8. The field effect transistor according to claim 2, wherein the energy width (E₀) on the non-localized level of the semiconductor layer is 14 meV or less.

9. The field effect transistor according to claim 2, wherein the surface roughness (RMS) of the semiconductor layer is 1 nm or less.

10. The field effect transistor according to claim 2, wherein the semiconductor layer comprises one or more elements selected from the group consisting of Sn, Ge, Si, Ti, Zr and Hf in an amount of 100 to 10,000 atomic ppm.

11. The field effect transistor according to claim 2, wherein the semiconductor layer is an amorphous film which has an electron carrier concentration of 10¹³ to 10¹⁸/cm³ and a band gap of 2.0 to 6.0 eV.

12. The field effect transistor according to claim 2, wherein the semiconductor layer is a nondegenerate semiconductor.

13. A display comprising the field effect transistor of claim 2.

14. A target for a semiconductor layer comprising a composite oxide which comprises In and Zn in an atomic ratio of In/(In+Zn) of 0.2 to 0.8,

the bulk resistance of the target being 20 mΩ

or less and

the transverse rupture strength of the target being 8 kg/mm² or more.

15. The target for a semiconductor layer according to claim 14, wherein the target further comprises one or more elements selected from the group consisting of Sn, Ge, Si, Ti, Zr and Hf in an amount of 100 to 10,000 atomic ppm.

16. A method for producing a field effect transistor comprising forming a semiconductor layer by DC or AC sputtering with the target according to claim 14, and subjecting the semiconductor layer to a heat treatment at 70 to 350°

C.