×

TERMINATION ARRANGEMENT FOR VERTICAL MOSFET

  • US 20130313636A1
  • Filed: 05/22/2012
  • Published: 11/28/2013
  • Est. Priority Date: 05/22/2012
  • Status: Active Grant
First Claim
Patent Images

1. A transistor device comprising:

  • an active region, including at least one vertical channel transistor cell, and a termination region electrically coupled to the active region;

    a semiconductor layer disposed at the active region and the termination region;

    a gate insulator layer disposed partly on a portion of the vertical channel transistor cell and partly on a portion of the semiconductor layer at the termination region; and

    a field insulator layer disposed on another portion of the semiconductor layer at the termination region and forming a step structure on the other portion of the semiconductor layer at the termination region.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×