FORMING FACET-LESS EPITAXY WITH A CUT MASK

• US 20130313647A1
• Filed: 05/23/2012
• Published: 11/28/2013
• Est. Priority Date: 05/23/2012
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Aquilino, Michael Vincent, Kim, Byeong Yeol, Li, Ying, Radens, Carl John
• Granted Patent: US 8,658,486 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A method of forming a semiconductor structure on a substrate is provided. The method may include preparing a continuous active layer on a region of the substrate and depositing a first raised epitaxial layer on a first region of the continuous active layer. A second raised epitaxial layer is also deposited on a second region of the continuous active layer such that the first raised epitaxial layer is in close proximity to the second raised epitaxial layer. A mask may be used to etch a trench structure into the continuous active layer at both the first and the second raised epitaxial layer, whereby the etched trench structure is filled with isolation material for electrically isolating the first raised epitaxial layer from the second raised epitaxial layer.

Claims

1. A method of forming a semiconductor structure on a substrate, the method comprising:

preparing a continuous active layer on a region of the substrate;

depositing a first raised epitaxial layer on a first region of the continuous active layer;

depositing a second raised epitaxial layer on a second region of the continuous active layer, wherein the first raised epitaxial layer is in close proximity to the second raised epitaxial layer;

forming, prior to the depositing of the first and the second raised epitaxial layer, transistor gate structures associated with the first raised epitaxial layer and the second raised epitaxial layer on the continuous active layer;

etching, using a first cut mask, a dummy gate region associated with the formed transistor gate structures prior to the depositing of the first and the second raised epitaxial layer on a continuous active region within the continuous active layer;

etching, using a second cut mask, a trench structure into the continuous active layer at both the first and the second raised epitaxial layer; and

filling the trench structure with isolation material, the isolation material electrically isolating the first raised epitaxial layer from the second raised epitaxial layer.

3. The method of claim 1, wherein the second cut mask overlaps the etched dummy gate region provided by the first cut mask.

4. The method of claim 1, wherein depositing the first raised epitaxial layer comprises depositing a first raised source/drain layer of a first transistor.

5. The method of claim 4, wherein depositing the second raised epitaxial layer comprises depositing a second raised source/drain layer of a second transistor next to said first transistor.

6. The method of claim 1, wherein filling the trench structure with isolation material comprises filling the trench structure with high density plasma (HDP) oxide.

7. The method of claim 1, wherein depositing the first raised epitaxial layer on a first region of the continuous active layer comprises forming a first facet-less raised epitaxial layer of a first transistor, wherein the first facet-less raised epitaxial layer is facet-less at a first edge of the trench structure filled with isolation material.

8. The method of claim 7, wherein depositing the second raised epitaxial layer on a second region of the continuous active layer comprises forming a second facet-less raised epitaxial layer of a second transistor, wherein the second facet-less raised epitaxial layer is facet-less at a second edge of the trench structure filled with isolation material, the first and the second transistor being adjacent.

9. The method of claim 1, further comprising:

covering, prior to the etching using the second cut mask, the deposited first and the deposited second raised epitaxial layer with an interlayer dielectric (ILD) layer of insulation material under the second cut mask; and

opening, using the second cut mask, the trench structure in the interlayer dielectric (ILD) layer of insulation material above the deposited first and the deposited second raised epitaxial layer.

10. The method of claim 9, wherein:

depositing the first raised epitaxial layer on a first region of the continuous active layer comprises depositing a first facet-less raised epitaxial layer of a first transistor, wherein the first facet-less raised epitaxial layer is facet-less at a first edge of the trench structure filled with isolation material; and

depositing the second raised epitaxial layer on a second region of the continuous active layer comprises depositing a second facet-less raised epitaxial layer of a second transistor, wherein the second facet-less raised epitaxial layer is facet-less at a second edge of the trench structure filled with isolation material, the first and the second transistor being adjacent.

11. The method of claim 9, further comprising, prior to the depositing of the first and the second raised epitaxial layer:

forming transistor gate structures associated with the first raised epitaxial layer and the second raised epitaxial layer on the continuous active layer; and

etching, using the first cut mask, a dummy transistor gate associated with the formed transistor gate structures.

12. The method of claim 9, wherein depositing the first raised epitaxial layer comprises depositing a first raised source/drain layer of a first transistor.

13. The method of claim 12, wherein depositing the second raised epitaxial layer comprises depositing a second raised source/drain layer of a second transistor.

14. The method of claim 9, wherein filling the trench structure with isolation material comprises filling the trench structure with a silicon oxide insulator material.

15. The method of claim 9, wherein the isolation material is different than the interlayer dielectric (ILD) material, and wherein the isolation material has a different etch-rate from that of the interlayer dielectric material (ILD).

2. (canceled)

16. A method of forming a semiconductor structure on a substrate, the method comprising:

preparing a continuous active layer on a region of the substrate;

depositing a first raised epitaxial layer on a first region of the continuous active layer, wherein the first raised epitaxial layer corresponds to a first device;

depositing a second raised epitaxial layer on a second region of the continuous active layer, the second raised epitaxial layer corresponding to a second device, wherein the first raised epitaxial layer is in close proximity to the second raised epitaxial layer;

forming, prior to the depositing of the first and the second raised epitaxial layer, transistor gate structures associated with the first raised epitaxial layer and the second raised epitaxial layer on the continuous active layer;

etching, using a first cut mask, a dummy gate region associated with the formed transistor gate structures prior to the depositing of the first and the second raised epitaxial layer on a continuous active region within the continuous active layer; and

electrically connecting the first raised epitaxial layer and the second raised epitaxial layer for connecting the first and the second device.

17. (canceled)

18. A semiconductor structure comprising:

a substrate;

an active layer located on a region of the substrate;

a trench structure extending into the active layer;

a first raised epitaxial layer located on top of a first region of the active layer to a left side of the trench structure, the first raised epitaxial layer and the trench structure sharing a portion of a first sidewall, wherein the first raised epitaxial layer is facet-less at the first sidewall; and

a second raised epitaxial layer located on top of a second region of the active layer to a right side of the trench structure, the second raised epitaxial layer and the trench structure sharing a portion of a second sidewall, wherein the second raised epitaxial layer is facet-less at the second sidewall, and

wherein the trench structure is filled with isolation material for electrically isolating the first raised epitaxial layer from the second raised epitaxial layer.

19. The structure of claim 18, further comprising:

a first transistor gate structure located on the active layer and corresponding to the first raised epitaxial layer; and

a second transistor gate structure located on the active layer and corresponding to the second raised epitaxial layer.

20. The structure of claim 18, further comprising:

an interlayer dielectric (ILD) layer of insulation material covering the first raised epitaxial layer and the second raised epitaxial layer, wherein the trench structure is formed in the interlayer dielectric (ILD) layer of insulation material.