Isolated Through Silicon Via and Isolated Deep Silicon Via Having Total or Partial Isolation

• US 20130313682A1
• Filed: 05/01/2013
• Published: 11/28/2013
• Est. Priority Date: 05/25/2012
• Status: Active Grant

• Current Assignee: Newport Fab, LLC (Tower Semiconductor Limited)
• Original Assignee: Newport Fab, LLC (Tower Semiconductor Limited)
• Inventors: Jebory, Hadi, Howard, David J., Racanelli, Marco, Preisler, Edward
• Granted Patent: US 9,673,081 B2
• Time in Patent Office: Days
• US Class Current: 257/544
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Disclosed are a structure for improving electrical signal isolation in a semiconductor substrate and an associated method for the structure'"'"'s fabrication. The structure includes a deep trench having sidewalls disposed in the semiconductor substrate. An isolation region may be formed along at least an upper portion of the sidewalls of the deep trench, and a metallic filler may be disposed in the deep trench. The isolation region may include a PN junction formed by one or more of ion implantation and annealing, deposition of highly doped polysilicon and out diffusion, and gas phase doping and annealing. In the alternative, the isolation region may be a dielectric isolation region formed by one or more of uniform dielectric deposition, partial dieletric deposition, and dielectric deposition by ionic reaction.

Claims

1. A method for improving electrical signal isolation in a semiconductor substrate, said method comprising:

fabricating a deep trench having sidewalls into said semiconductor substrate;

forming an isolation region along at least an upper portion of said sidewalls of said deep trench.

2. The method of claim 1, wherein said deep trench is part of a through silicon via.

3. The method of claim 1, wherein said deep trench is part of a deep silicon via.

4. The method of claim 1, wherein said forming said isolation region comprises applying a doping implant to said deep trench at a non-perpendicular angle to form a PN junction in said upper portion of said sidewalls of said deep trench.

5. The method of claim 1, wherein said forming said isolation region comprises depositing a layer of doped polysilicon on said sidewalls of said deep trench.

6. The method of claim 5, further comprising annealing said semiconductor substrate to provide out-diffusion of dopants from said doped polysilicon into said sidewalls of said deep trench.

7. The method of claim 1, wherein said forming said isolation region comprises applying a gas flow providing a dopant to said deep trench, said dopant having a conductivity type opposite of said semiconductor substrate to form a PN junction in said sidewalls of said deep trench.

8. The method of claim 7, further comprising annealing said semiconductor substrate.

9. The method of claim 1, wherein said forming said isolation region comprises depositing a dielectric layer on said sidewalls of said deep trench.

10. The method of claim 1, wherein said forming said isolation region comprises exposing said deep trench to a gas flow comprising ions to react with said semiconductor substrate to form a dielectric layer on said sidewalls of said deep trench.

11. The method of claim 1, wherein said isolation region extends to all portions of said sidewalls of said deep trench.

12. The method of claim 1, further comprising filling said deep trench with a metallic filler.

13. A structure for improving electrical signal isolation in a semiconductor substrate, said structure comprising:

a deep trench having sidewalls disposed in said semiconductor substrate;

an isolation region formed along at least an upper portion of said sidewalls of said deep trench.

14. The structure of claim 13, wherein said deep trench is part of a through silicon via.

15. The structure of claim 13, wherein said deep trench is part of a through silicon via.

16. The structure of claim 13, wherein said isolation region comprises a PN junction formed in said upper portion of said sidewalls of said deep trench.

17. The structure of claim 13, wherein said isolation region comprises a PN junction formed by depositing a layer of doped polysilicon on said sidewalls of said deep trench.

18. The structure of claim 13, wherein said isolation region comprises a PN junction formed by applying a gas flow comprising a dopant to said deep trench, said dopant having a conductivity type opposite of said semiconductor substrate.

19. The structure of claim 13, wherein said isolation region comprises a dielectric layer formed by exposing said deep trench to a gas flow comprising ions to react with said semiconductor substrate to form said dielectric layer.

20. The structure of claim 13, wherein said isolation region extends to all portions of said sidewalls of said deep trench.