MEASUREMENT DEVICE

• US 20130314074A1
• Filed: 05/16/2013
• Published: 11/28/2013
• Est. Priority Date: 05/23/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takahashi, Kei, Inoue, Noboru
• Granted Patent: US 9,817,032 B2
• Time in Patent Office: Days
• US Class Current: 324/110
• CPC Class Codes: G01R 1/06766 Input circuits therefor
• CPC Class Codes: G01R 1/36 Overload-protection arrangements or circuits for electric measuring instruments
• CPC Class Codes: G01R 31/27 Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements testing printed circuit boards G01R31/2801
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309

Abstract

To provide a measurement device which allows long-term accurate measurement of voltage without adversely affecting a device under test, by ensuring a predetermined level of resistance to ESD and reducing leakage current. A measurement device includes a probe needle for contacting a device under test, a first FET for detecting voltage of the device under test, and a protection circuit for protecting the first FET from static electricity. The protection circuit includes a second FET having an oxide semiconductor film as a channel formation region.

Claims

1. A measurement device comprising:

a probe;

a first transistor electrically connected to the probe and configured to detect voltage of a device under test; and

a protection circuit electrically connected to the first transistor, wherein the protection circuit comprises a second transistor comprising an oxide semiconductor film,

wherein a channel formation region of the second transistor is formed in the oxide semiconductor film.

2. The measurement device according to claim 1, wherein leakage current of the second transistor in an off state is less than or equal to 10⁻

24 A.

3. The measurement device according to claim 1,

wherein an insulating film is provided over the first transistor,

wherein the second transistor is provided over the insulating film, and

wherein a channel formation region of the first transistor comprises silicon.

16. The measurement device according to claim 1, wherein the probe has a needle-like shape.

4. A measurement device comprising:

a probe;

a first transistor;

a second transistor;

a third transistor; and

a first line configured to supply a high power source potential, wherein a gate of the first transistor is electrically connected to the probe, a gate and a drain of the second transistor, and a source of the third transistor,

wherein a drain of the first transistor is electrically connected to the first line,

wherein a source of the first transistor is electrically connected to a gate and a drain of the third transistor,

wherein a source of the second transistor is electrically connected to the first line,

wherein the second transistor and the third transistor each comprise an oxide semiconductor film, and

wherein a channel formation region of each of the second transistor and the third transistor is formed in the oxide semiconductor film.

5. The measurement device according to claim 4, further comprising:

a fourth transistor;

a second line configured to supply a low power source potential; and

a wiring configured to supply a bias potential, wherein the source of the first transistor is electrically connected to a drain of the fourth transistor,

wherein the gate and the drain of the third transistor are electrically connected to the second line,

wherein a gate of the fourth transistor is electrically connected to the wiring, and

wherein a source of the fourth transistor is electrically connected to the second line.

6. The measurement device according to claim 4, wherein leakage current of the second transistor in an off state and leakage current of the third transistor in an off state are each less than or equal to 10⁻

24 A.

7. The measurement device according to claim 4,

wherein an insulating film is provided over the first transistor,

wherein the second transistor and the third transistor are provided over the insulating film, and

wherein a channel formation region of the first transistor comprises silicon.

8. The measurement device according to claim 5, wherein leakage current of the second transistor in an off state and leakage current of the third transistor in an off state are each less than or equal to 10⁻

24 A.

9. The measurement device according to claim 5,

wherein an insulating film is provided over the first transistor and the fourth transistor,

wherein the second transistor and the third transistor are provided over the insulating film, and

wherein a channel formation region of each of the first transistor and the fourth transistor comprises silicon.

17. The measurement device according to claim 4, wherein the probe has a needle-like shape.

10. A measurement device comprising:

a probe;

a first transistor;

a second transistor;

a third transistor; and

a first line configured to supply a low power source potential, wherein a gate of the first transistor is electrically connected to the probe, a gate and a drain of the second transistor, and a source of the third transistor,

wherein a drain of the first transistor is electrically connected to the first line,

wherein a source of the first transistor is electrically connected to a source of the second transistor,

wherein a drain of the third transistor is electrically connected to the first line,

wherein the second transistor and the third transistor each comprise an oxide semiconductor film, and

wherein a channel formation region of each of the second transistor and the third transistor is formed in the oxide semiconductor film.

11. The measurement device according to claim 10, further comprising:

a fourth transistor;

a second line configured to supply a high power source potential; and

a wiring configured to supply a bias potential, wherein the source of the first transistor is electrically connected to a drain of the fourth transistor,

wherein the source of the second transistor is electrically connected to the second line,

wherein a gate of the third transistor is electrically connected to the first line,

wherein a gate of the fourth transistor is electrically connected to the wiring, and

wherein a source of the fourth transistor is electrically connected to the second line.

12. The measurement device according to claim 10, wherein leakage current of the second transistor in an off state and leakage current of the third transistor in an off state are each less than or equal to 10⁻

24 A.

13. The measurement device according to claim 10,

wherein an insulating film is provided over the first transistor, wherein the second transistor and the third transistor are provided over the insulating film, and

wherein a channel formation region of the first transistor comprises silicon.

14. The measurement device according to claim 11, wherein leakage current of the second transistor in an off state and leakage current of the third transistor in an off state are each less than or equal to 10⁻

24 A.

15. The measurement device according to claim 11,

wherein an insulating film is provided over the first transistor and the fourth transistor,

wherein the second transistor and the third transistor are provided over the insulating film, and

wherein a channel formation region of each of the first transistor and the fourth transistor comprises silicon.

18. The measurement device according to claim 10, wherein the probe has a needle-like shape.