MEMORY SYSTEM

• US 20130314989A1
• Filed: 03/04/2013
• Published: 11/28/2013
• Est. Priority Date: 05/25/2012
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Wakisaka, Mio, Irieda, Shigefumi
• Application Number:
  US13/784,498
• Publication Number:
  US 20130314989A1
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

A memory system includes nonvolatile memory cells each configured to store more than one bit of data, dummy memory cells adjacent to the nonvolatile memory cells, and a control section that applies a read voltage to the nonvolatile memory cells while a first voltage is applied to a gate of the dummy memory cells, when data of the nonvolatile memory cells are read out. The first voltage is higher than a second voltage for turning on the nonvolatile memory cells whose data are not read during the read out.

Claims

1. A memory system, comprising:

nonvolatile memory cells each configured to store more than one bit of data;

dummy memory cells; and

a controller configured to control application of voltages to gates of the nonvolatile memory cells and the dummy memory cells, such that during an operation to read data from a group of the nonvolatile memory cells that are adjacent to the dummy memory cells, a read voltage is applied to the gates of the nonvolatile memory cells in the group while a first voltage is applied to gates of the dummy memory cells and a second voltage is applied to the other groups of the nonvolatile memory cells, the first voltage being higher than the second voltage.

2. The memory system according to claim 1, wherein

during the operation to read data from the group of the nonvolatile memory cells that are adjacent to the dummy memory cells, the read voltage is applied to the gates of the nonvolatile memory cells in the group while the first voltage is applied to gates of the dummy memory cells and the second voltage is applied to the other groups of the nonvolatile memory cells, in response to determining that the operation to read data from the group of the nonvolatile memory cells results in an error that is not correctable by error correction coding.

3. The memory system according to claim 1, wherein

during the operation to read data from the group of the nonvolatile memory cells that are adjacent to the dummy memory cells, the read voltage is applied to the gates of the nonvolatile memory cells in the group while the first voltage is applied to gates of the dummy memory cells and the second voltage is applied to the other groups of the nonvolatile memory cells, in response to determining that the group of the nonvolatile memory cells has undergone erase and program operations a number of times that exceed a predetermined number.

4. The memory system according to claim 1, wherein

during an operation to read data from another group of the nonvolatile memory cells that are not adjacent to the group of the nonvolatile memory cells, the read voltage is applied to the gates of the nonvolatile memory cells in the another group while the second voltage is applied to the other groups of the nonvolatile memory cells.

5. The memory system according to claim 4, wherein

the first voltage is applied to gates of the nonvolatile memory cells that are adjacent to the nonvolatile memory cells in the another group on the side of the dummy memory cells and is not applied to gates of the nonvolatile memory cells that are adjacent to the nonvolatile memory cells in the another group on the side opposite the dummy memory cells.

6. The memory system according to claim 1, wherein

if data stored in the dummy memory cells are first data, the read voltage is applied to the gates of the nonvolatile memory cells in the group while applying a third voltage that is higher than the second voltage to the gates of the dummy memory cells, and

if data stored in the dummy memory cells are second data, the read voltage is applied to the gates of the nonvolatile memory cells in the group while applying a fourth voltage that is higher than the third voltage to the gates of the dummy memory cells.

7. The memory system according claim 6, wherein

the controller maintains a table that associates voltages to be applied to the gates of the dummy memory cells with data stored therein.

8. A memory system, comprising:

multiple memory strings each including a plurality of nonvolatile memory cells connected serially between first and second selection transistors, each memory string including a dummy memory cell adjacent to the first selection transistor and each nonvolatile memory cell configured to store more than one bit of data;

a plurality of word lines, each word line connected to a gate of a different memory cell in each of the memory strings, the word lines including a dummy word line connected to a gate of the dummy memory cell in each of the memory strings; and

a controller configured to control application of voltages to the gates of the nonvolatile memory cells through the word lines, such that during an operation to read data from a group of the nonvolatile memory cells connected to a word line that is adjacent to the dummy word line, a read voltage is applied to the word line that is adjacent to the dummy word line while a first voltage is applied to the dummy word line, and a second voltage is applied to the other word lines, the first voltage being higher than the second voltage.

9. The memory system according to claim 8, wherein

during the operation to read data from the group of the nonvolatile memory cells, the read voltage is applied to the word line that is adjacent to the dummy word line while the first voltage is applied to the dummy word line and the second voltage is applied to the other word lines, in response to determining that the operation to read data from the group of the nonvolatile memory cells results in an error that is not correctable by error correction coding.

10. The memory system according to claim 8, wherein

during the operation to read data from the group of the nonvolatile memory cells, the read voltage is applied to the word line that is adjacent to the dummy word line while the first voltage is applied to the dummy word line and the second voltage is applied to the other word lines, in response to determining that the group of the nonvolatile memory cells has undergone erase and program operations a number of times that exceed a predetermined number.

11. The memory system according to claim 8, wherein

during an operation to read data from another group of the nonvolatile memory cells connected to a first word line, which is one of the word lines not adjacent to the dummy word line, the read voltage is applied to the first word line while the first voltage is applied to a second line that is adjacent to the first word line and the second voltage is applied to the other word lines.

12. The memory system according to claim 11, wherein the second word line is located on a side of the first word line that is closer to the dummy word line.

13. The memory system according to claim 8, wherein

if data stored in the dummy memory cells are first data, the read voltage is applied to the word line that is adjacent to the dummy word line while applying a third voltage that is higher than the second voltage to the dummy word line, and

if data stored in the dummy memory cells are second data, the read voltage is applied to the word line that is adjacent to the dummy word line while applying a fourth voltage that is higher than the third voltage to the dummy word line.

14. The memory system according claim 13, wherein

the controller maintains a table that associates voltages to be applied to the dummy word line with data stored in the dummy memory cells.

15. In a memory system having multiple memory strings each including a plurality of nonvolatile memory cells connected serially between first and second selection transistors, each memory string including a dummy memory cell adjacent to the first selection transistor and each nonvolatile memory cell configured to store more than one bit of data, and a plurality of word lines, each word line connected to agate of a different memory cell in each of the memory strings, the word lines including a dummy word line connected to a gate of the dummy memory cell in each of the memory strings, a method of controlling voltages applied to the word lines during an operation to read data from a group of the nonvolatile memory cells connected to a word line that is adjacent to the dummy word line, comprising:

applying a read voltage to the word line that is adjacent to the dummy word line while applying a first voltage to the dummy word line and a second voltage to the other word lines,

wherein the first voltage is higher than the second voltage.

16. The method of claim 15, further comprising:

determining that the operation to read data from the group of the nonvolatile memory cells results in an error that is not correctable by error correction coding.

17. The method of claim 15, further comprising:

determining that the group of the nonvolatile memory cells has undergone erase and program operations a number of times that exceed a predetermined number.

18. The method of claim 15, further comprising:

applying the read voltage to a first word line, which is one of the word lines not adjacent to the dummy word line while applying the first voltage to a second line that is adjacent to the first word line and the second voltage to the other word lines.

19. The method of claim 18, wherein the second word line is located on a side of the first word line that is closer to the dummy word line.

20. The method of claim 15, further comprising:

if data stored in the dummy memory cells are first data, applying the read voltage to the word line that is adjacent to the dummy word line while applying a third voltage that is higher than the second voltage to the dummy word line; and

if data stored in the dummy memory cells are second data, applying the read voltage to the word line that is adjacent to the dummy word line while applying a fourth voltage that is higher than the third voltage to the dummy word line.