SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF
First Claim
1. A semiconductor device comprising:
- a first circuit configured to control a state including a driving voltage and a clock frequency of a processor core;
a first memory circuit and a second memory circuit which store state data;
a second circuit generating a power supply voltage and a third circuit generating a clock, the second circuit and the third circuit being electrically connected to the first circuit; and
the processor core electrically connected to the second circuit and the third circuit through a switch,wherein the processor cores comprises;
a first memory; and
a second memory transmitting and receiving data to/from the first memory.
1 Assignment
0 Petitions
Accused Products
Abstract
A semiconductor device in which a nonvolatile memory can normally operate and power saving can be performed with a P-state function, and a driving method of the semiconductor device are provided. The semiconductor device includes: a first circuit configured to control a state including a driving voltage and a clock frequency of a processor core; a first memory circuit and a second memory circuit which store state data; a second circuit generating a power supply voltage and a third circuit generating a clock which are electrically connected to the first circuit; and the processor core electrically connected to the second circuit and the third circuit through a switch. The processor cores includes: a volatile memory; and a nonvolatile memory transmitting and receiving data to/from the first memory.
-
Citations
20 Claims
-
1. A semiconductor device comprising:
-
a first circuit configured to control a state including a driving voltage and a clock frequency of a processor core; a first memory circuit and a second memory circuit which store state data; a second circuit generating a power supply voltage and a third circuit generating a clock, the second circuit and the third circuit being electrically connected to the first circuit; and the processor core electrically connected to the second circuit and the third circuit through a switch, wherein the processor cores comprises; a first memory; and a second memory transmitting and receiving data to/from the first memory. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A driving method of a semiconductor device, comprising the steps of:
-
operating a processor core with a first state; performing an off operation; and performing an on operation, wherein the off operation comprises the steps of; keeping the first state or changing the first state into a second state; reading data from a first memory in the processor core; writing the data to a second memory in the processor core; and turning off the processor core, and wherein the on operation comprises the steps of; keeping a state in the off operation or changing the state in the off operation into a third state; turning on the processor core; reading the data from the second memory; writing the data to the first memory; and changing the state in the off operation or the third state into the first state. - View Dependent Claims (8, 9, 10, 11, 12)
-
-
13. A driving method of a semiconductor device, comprising the steps of:
-
storing first state data including a driving voltage and a clock frequency supplied to a processor core in a first memory device; performing an off operation; and performing an on operation, wherein, in the off operation, a first circuit configured to control a state receives an instruction for the off operation, the first state data is stored in a second memory device, the first state data stored in the first memory device is rewritten into second state data, the driving voltage and the clock frequency of the processor core are changed in accordance with the second state data, the first circuit requests an instruction for the off operation from a power gating circuit, data stored in a first memory in the processor core is read, the data is written to a second memory in the processor core, and electrical connection between the processor core and each of a second circuit generating a power supply voltage and a third circuit generating a clock is broken. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
-
Specification