FIN ISOLATION FOR MULTIGATE TRANSISTORS

• US 20130316513A1
• Filed: 05/23/2012
• Published: 11/28/2013
• Est. Priority Date: 05/23/2012
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: BASKER, VEERARAGHAVAN S., LEOBANDUNG, EFFENDI, YAMASHITA, TENKO, YEH, CHUN-CHEN
• Application Number:
  US13/478,976
• Publication Number:
  US 20130316513A1
• Time in Patent Office: Days
• US Class Current: 438/400
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Multigate transistor devices and methods of their fabrication are disclosed. In one method, a substrate including a semiconductor upper layer and a lower layer beneath the upper layer is provided. The lower layer has a rate of transformation into a dielectric that is higher than a rate of transformation into a dielectric of the upper layer when the upper and lower layers are subjected to dielectric transformation conditions. Fins are formed in the upper layer, and the lower layer beneath the fins is transformed into a dielectric material to electrically isolate the fins. In addition, a gate structure is formed over the fins to complete the multigate transistor device.

Claims

1. A method for fabricating a multigate transistor device comprising:

providing a substrate including a semiconductor upper layer and a lower layer beneath the upper layer, wherein the lower layer has a rate of transformation into a dielectric that is higher than a rate of transformation into a dielectric of the upper layer when the upper and lower layers are subjected to dielectric transformation conditions;

forming fins in the upper layer;

transforming, after said forming, the lower layer beneath the fins into a dielectric material by germanium condensation of at least a portion of the lower layer to electrically isolate the fins; and

forming a gate structure over the fins to complete the multigate transistor device.

2. The method of claim 1, wherein the lower layer has a rate of oxidation that is higher than a rate of oxidation of the upper layer when the upper and lower layers are subjected to oxidation conditions.

3. The method of claim 2, wherein the transforming comprises oxidizing the lower layer beneath the fins to electrically isolate the fins.

4. The method of claim 3, wherein the upper layer is a silicon layer and the lower layer is a silicon-germanium layer.

5. The method of claim 1, further comprising:

forming spacers on sidewalls of the fins prior to said transforming.

6. The method of claim 5, wherein the forming a gate structure further comprises removing the spacers.

7. The method of claim 6, wherein the transforming comprises oxidizing the lower layer and wherein the spacers protect the fins from oxidation.

8. A method for fabricating a multigate transistor device comprising:

forming recesses in a lower layer that is beneath a semiconductor upper layer in which fins are formed, wherein the recesses are disposed between the fins of the upper layer;

transforming the recessed lower layer beneath the fins into a first dielectric material to electrically isolate the fins;

forming, after the transforming, a second dielectric material in the recesses such that top surfaces of regions of the first dielectric material that are beneath the fins are higher than top surfaces of the second dielectric material; and

forming a gate structure over the fins to complete the multigate transistor device.

9. The method of claim 8, wherein the density of the first dielectric material is greater than the density of the second dielectric material.

10. The method of claim 8, wherein the first dielectric material has a higher resistance to wet etching than the second dielectric material.

11. The method of claim 8, wherein the lower layer in which the recesses are formed is a silicon-germanium layer and wherein the upper layer is a silicon layer.

12. The method of claim 8, the transforming comprises oxidizing the lower layer beneath the fins to electrically isolate the fins.

13. The method of claim 8, further comprising:

forming spacers on sidewalls of the fins prior to said transforming.

14. The method of claim 13, wherein the forming a gate structure further comprises removing the spacers.

15. A method for fabricating a multigate transistor device comprising:

providing a substrate including a semiconductor upper layer and a lower layer beneath the upper layer, wherein the lower layer has a rate of transformation into a dielectric that is higher than a rate of transformation into a dielectric of the upper layer when the upper and lower layers are subjected to dielectric transformation conditions;

forming recesses in the lower layer such that the recesses are disposed between the fins of the upper layer;

transforming the recessed lower layer beneath the fins into a first dielectric material to electrically isolate the fins such that a width of a region of the first dielectric material beneath a given fin of said fins is at most equal to a width of the given fin;

depositing a second dielectric material in the recesses; and

forming a gate structure over the fins to complete the multigate transistor device.

16. The method of claim 15, wherein the lower layer has a rate of oxidation that is higher than a rate of oxidation of the upper layer when the upper and lower layers are subjected to oxidation conditions.

17. The method of claim 16, wherein the transforming comprises oxidizing the lower layer beneath the fins to electrically isolate the fins.

18. The method of claim 17, wherein the upper layer is a silicon layer and the lower layer is a silicon-germanium layer.

19. The method of claim 15, wherein the density of the first dielectric material is greater than the density of the second dielectric material.

20. The method of claim 15, wherein the first dielectric material has a higher resistance to wet etching than the second dielectric material.