MEMORY SYSTEM IN WHICH EXTENDED FUNCTION CAN EASILY BE SET

• US 20130318281A1
• Filed: 08/01/2013
• Published: 11/28/2013
• Est. Priority Date: 02/04/2011
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: FUJIMOTO, Akihisa, Sakamoto, Hiroyuki
• Granted Patent: US 9,104,539 B2
• Time in Patent Office: Days
• US Class Current: 711/102
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00

Abstract

According to one embodiment, a memory system, such as a SDIO card, includes a nonvolatile semiconductor memory device, a control section, a memory, an extended function section, and an extension register. The extended function section is controlled by the control section. A first command reads data from the extension register in units of given data lengths. A second command writes data to the extension register in units of given data lengths. A extension register includes a first area, and second area different from the first area, information configured to specify a type of the extended function and controllable driver, and address information indicating a place to which the extended function is assigned, the place being on the extension register, are recorded in the first area, and the second area includes the extended function.

Claims

1. A memory system comprising:

a nonvolatile semiconductor memory device;

a control section configured to control the nonvolatile semiconductor memory device;

a memory serving as a work area connected to the control section;

an extended function section to be controlled by the control section; and

an extension register provided on the memory or on the control section, the extension register being capable of defining an interface controlling an extended function of the extended function section, wherein

the control section processes a first command to read the extension register in units of predetermined data lengths, and a second command to write data to the extension register in units of predetermined data lengths,

the extension register includes a first area, and a second area different from the first area, information configured to specify a type of the extended function and a controllable driver, and address information indicating a place to which the extended function is assigned, the place being on the extension register, are recorded in the first area, and the second area includes the extended function.

2. The system according to claim 1, wherein

each of the first and second commands comprises, as arguments, an address field of a length necessary to access data in one specific page of the extension register space constituted of a plurality of pages, and a length field indicating an effective data length,

a value of the address field of each of the first and second commands includes first and second operation modes,

the first operation mode of the first command corresponds to a read operation of reading data of a data length indicated by the length field from a position of the extension register indicated by the address field, and

the first operation mode of the second command corresponds to a write operation of writing data of a data length indicated by the length field to a position of the extension register indicated by the address field, and in the second operation mode of each the first and second commands, a specific address indicated by the address field is interpreted as a data port of the extension register, and data transfer between the data port and the extended function section associated with the data port is carried out.

3. The system according to claim 2, wherein

in the first operation mode of the first command, data items read from a designated page of the extension register are arranged from a head of a data block, and

in the first operation mode of the second command, data items arranged from the head of the data block are written to the extension register at a designated position in a designated page of the extension register by a designated length.

4. The system according to claim 2, wherein

the second command includes, in an argument, a bit used to select whether or not mask write is to be carried out, when mask write is not carried out, the length field indicates an effective write data length, and when mask write is carried out, the write data length becomes a fixed value, the length field indicates mask information used to select whether write is to be carried out in units of one bit or original data is to be held, and the mask information is of the same length as the fixed data length.

5. The system according to claim 2, further comprising an extension register set assigned to each of a plurality of functions, wherein

a value singly assigned to each of the functions is displayed in the function identification information in the first area, and

arguments of each of the first and second commands include the function identification information and, when the function identification information is in correspondence with an extension register set specified by the address field, the command is executed.

6. The system according to claim 2, further comprising a third command used as a read command supporting fixed-length block transfer and multi-block transfer, and a fourth command used as a write command, wherein

each of the third and fourth commands includes an address field as an argument, data transfer is executed only when the address field designates a data port of the extension register, and a block count configured to designate a data transfer amount is set in advance to the extension register or is set in advance by a command to set a block count.

7. The system according to claim 6, further comprising an extension register set assigned to each of a plurality of functions, wherein

a value singly assigned to each of the functions is displayed in the function identification information in the first area, and

arguments of each of the third and fourth commands include the function identification information and, when the function identification information is in correspondence with an extension register set specified by the address field, the command is executed.

8. The system according to claim 1, wherein

a general information field which is a first area of the extension register includes a function identification code configured to recognize a standard extended function, manufacturer identification information configured to recognize a manufacturer, and a function identification information for identifying classification for an extended function, wherein the general information field is used as an information for selecting a general-purpose driver or a dedicated driver.

9. The system according to claim 8, further comprising a host including a host driver, wherein

the host driver uses the first command to read the function identification code, the manufacturer identification information, and the function identification information which are described in the first area of the extension register, and specify a usable general-purpose function driver or a dedicated function driver and, when a driver exists, the host loads the driver, and the function driver initializes the extended function.

10. The system according to claim 9, wherein

the host driver delivers position information about the extension register assigned to the extended function to the loaded function driver from the general information field, thereby making the extended function controllable even when the extended function is arranged at an arbitrary position.

11. The system according to claim 2, further comprising:

a fifth command which enables read/write supporting variable-length block transfer, and multi-block transfer;

a sixth command which enables read/write of 1-byte data by the argument and the response; and

a plurality of function areas which can be accessed by the fifth and sixth commands, wherein

the first area is assigned to part of the leading function area, the second area is assigned to the other part of the function area, and an extension register area which can be accessed by the fifth and sixth commands can also be accessed by the first and second commands.

12. The system according to claim 9, wherein

the host driver accesses the extension register by the first and second commands or by the third and fourth commands in the first operation mode, and carries out data transfer between the host driver and the extended function section in the second operation mode.

13. The system according to claim 9, wherein

the host driver specifies a certain function from a plurality of multi-function devices by using address information configured to specify a memory or a device, and function identification information including a value singly assigned to each function read from the first area.

14. The system according to claim 9, wherein

the host driver selects one of a plurality of buffers on the basis of the function identification information including a value singly assigned to each function read from the first area, the plurality of buffers arranged in one-to-one correspondence with a plurality of function devices, and the function identification information set to the first command, the second command, the third command or the fourth command.