PROCESSOR NOISE MITIGATION USING DIFFERENTIAL CRITICAL PATH MONITORING

• US 20130318364A1
• Filed: 05/24/2012
• Published: 11/28/2013
• Est. Priority Date: 05/24/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Berry, Robert W. Jr., Floyd, Michael S., Pennington, Ryan J., Pena, Jarom, Sherry, Catherine
• Granted Patent: US 9,164,563 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 11/3062 where the monitored property is the power consumption power management in a computing system G06F1/3203

Abstract

An approach for power supply noise mitigation on a processor is provided. In one aspect, the approach comprises a central computing unit operatively coupled to the processor to execute program operations. The approach further comprises a calibration circuit adapted to determine a first threshold on the processor to be used for comparison performed dynamically through the use of a detection circuit. A detection circuit adapted to dynamically monitor system operation of the processor and indicate if the first threshold is violated and a counting circuit adapted to prevent voltage from drooping if one or more voltage sensing measurements violates the first threshold are also provided.

Claims

1. A method for mitigating power supply noise in a processor, the method comprising the steps of:

a calibration circuit executing a pre-specified workload on a processor, wherein the pre-specified workload drives substantially the same power supply load to each core of the processor;

the calibration circuit determining a first threshold to be used for comparison performed dynamically by a detection circuit;

the detection circuit dynamically monitoring system operation of the processor and indicating if the first threshold is violated; and

responsive to the indication, the detection circuit adjusting an operational parameter of the processor to avoid system failure of the processor.

2. The method according to claim 1, wherein the first threshold is detected and recorded on the processor, and wherein the first threshold is determined using a correctly functioning power supply to detect inadequate power delivered to the processor.

3. The method according to claim 1, wherein the detection circuit is adapted to compare the first threshold against one or more operational margins monitored on the processor, and if the one or more operational margins violates the first threshold, the detection circuit is further adapted to perform an instruction interrupt which places the processor into a degraded performance mode.

4. The method according to claim 1, wherein the calibration circuit is adapted to determine multiple thresholds to support multiple corresponding operating clock frequencies during system operation of the processor.

5. The method according to claim 1, wherein the step of the detection circuit adjusting an operational parameter, further comprises the step of:

the detection circuit adjusting operational parameters for multiple operating modes on the processor; and

the detection circuit adjusting voltages, changing clock frequencies or throttling instruction rates on the processor.

6. The method according to claim 1, wherein the step of the calibration circuit determining a first threshold further comprises the step of:

the calibration circuit determining a range of jitter that occurs on the processor by detecting and recording, during a pre-determined time period, one or more voltage droops that occur within the processor as the first threshold.

7. The method according to claim 1, wherein the calibration circuit includes a monitoring circuit, and wherein the monitoring circuit comprises an edge detection circuit adapted to detect and record, during the pre-determined time period, one or more voltage droops that occur within the processor as the first threshold.

8. The method according to claim 1, wherein the detection circuit includes a droop threshold detect circuit adapted to dynamically monitor one or more operational margins during system operation of the processor, and wherein the droop threshold detect circuit is further adapted to determine if the one or more operational margins exceed the first threshold.

9. The method according to claim 1, further comprising:

a counting circuit receiving environmental parameters, timing margins, and an acceptable voltage range for critical paths of the processor;

the counting circuit executing a pre-specified voltage sensing workload on the processor for a sensing period of time, wherein varied voltage and frequency settings are maintained on the processor;

the counting circuit determining and recording, during system operation of the processor, a number of one or more voltage droops that occur within the processor as one or more voltage sensing measurements;

the counting circuit comparing the first threshold against the one or more voltage sensing measurements; and

the counting circuit sending a signal to the processor so as to prevent voltage on critical paths from drooping if the one or more voltage sensing measurements exceeds the first threshold.

10. The method according to claim 9, wherein the counting circuit comprises a comparator, and wherein the comparator is adapted to compare the first threshold against the one or more voltage sensing measurements.

11. An apparatus for mitigating power supply noise in a processor, the apparatus comprising:

a central computing unit for executing program operations, wherein the central computing unit is operatively coupled to the processor;

a calibration circuit adapted to determine a first threshold on the processor to be used for comparison performed dynamically through the use of a detection circuit;

a detection circuit adapted to dynamically monitor system operation of the processor and indicate if the first threshold is violated; and

a counting circuit adapted to prevent voltage from drooping if one or more voltage sensing measurements violates the first threshold.

12. The apparatus according to claim 11, wherein the calibration circuit includes a monitoring circuit, and wherein the monitoring circuit comprises an edge detection circuit adapted to detect and record, during a pre-determined time period, one or more voltage droops that occur within the processor as the first threshold, and wherein determination of the first threshold comprises:

the calibration circuit executing a pre-specified workload on the processor, wherein the pre-specified workload drives substantially the same power supply load to each core of the processor; and

the calibration circuit determining a range of jitter that occurs on the processor by detecting and recording, during the pre-determined time period, one or more voltage droops that occur within the processor as the first threshold.

13. The apparatus according to claim 11, wherein the first threshold is determined using a correctly functioning power supply to detect inadequate power delivered to the processor.

14. The apparatus according to claim 11, wherein the calibration circuit is adapted to determine multiple thresholds to support multiple corresponding operating clock frequencies during system operation of the processor.

15. The apparatus according to claim 11, wherein the detection circuit includes a droop threshold detect circuit adapted to dynamically monitor one or more operational margins during system operation of the processor, and wherein the droop threshold detect circuit is further adapted to determine if one or more operational margins violates the first threshold.

16. The apparatus according to claim 11, wherein the detection circuit is adapted to compare the first threshold against one or more operational margins monitored on the processor, and if the one or more operational margins violates the first threshold, the detection circuit is further adapted to perform an instruction interrupt which places the processor into a degraded performance mode.

17. The apparatus according to claim 11, wherein if the first threshold is violated, detection circuit is further adapted to adjust an operational parameter of the processor to avoid system failure or degradation of performance of the processor, and wherein adjustment of an operational parameter of the processor comprises:

the detection circuit adjusting operational parameters of multiple operating modes on the processor; and

the detection circuit adjusting voltages, changing clock frequencies of throttling instruction rates on the processor.

18. The apparatus according to claim 11, wherein the counting circuit is adapted to compare the first threshold against one or more voltage sensing measurements, and wherein determination of the one or more voltage sensing measurements comprises:

the counting circuit receiving environmental parameters, timing margins, and an acceptable voltage range for critical paths of the processor;

the counting circuit executing a pre-specified voltage sensing workload on the processor for a sensing period of time, wherein varied voltage and frequency settings are maintained on the processor;

the counting circuit determining and recording, during system operation of the processor, a number of one or more voltage droops that occur within the processor as one or more voltage sensing measurements;

the counting circuit comparing the first threshold against the one or more voltage sensing measurements; and

the counting circuit sending a signal to the processor so as to prevent voltage on critical paths from drooping if the one or more voltage sensing measurements exceeds the first threshold.

19. The apparatus according to claim 18, wherein the counting circuit comprises a comparator, and wherein the comparator is adapted to compare the first threshold against the one or more voltage sensing measurements.

20. The apparatus according to claim 11, wherein the counting circuit is adapted to clear drooping voltage on the processor once a pre-determined limit of drooping voltage is reached.