EMBEDDED PLANAR SOURCE/DRAIN STRESSORS FOR A FINFET INCLUDING A PLURALITY OF FINS

• US 20130320399A1
• Filed: 05/30/2012
• Published: 12/05/2013
• Est. Priority Date: 05/30/2012
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Chang, Paul, Guillorn, Michael A., Sleight, Jeffrey W., Chang, Josephine B.
• Granted Patent: US 9,024,355 B2
• Time in Patent Office: Days
• US Class Current: 257/190
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed. The semiconductor material layer is recessed employing the disposable gate structure and the gate spacer as an etch mask to form recessed semiconductor material portions. Embedded planar source/drain stressors are formed on the recessed semiconductor material portions by selective deposition of a second semiconductor material having a different lattice constant than the first semiconductor material. After formation of a planarization dielectric layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed employing the fin-defining mask structures as an etch mask. A replacement gate structure is formed on the plurality of semiconductor fins.

Claims

1. A semiconductor structure comprising:

a fin-containing semiconductor portion comprising a first semiconductor material and including a plurality of semiconductor fins, a first end portion, and a second end portion, wherein each semiconductor fin among said plurality of semiconductor fins is laterally spaced from each other or one another along a widthwise direction, and a lengthwise end of each of said plurality of semiconductor fins is adjoined to said first end portion and another lengthwise end of each of said plurality of semiconductor fins is adjoined to said second end portion, wherein each of said first end portion and said second end portion includes a proximal portion having a same height as said plurality of semiconductor fins and a distal portion having a lesser height than said plurality of semiconductor fins;

a first stress-generating semiconductor portion in contact with a sidewall of said proximal portion of said first end portion and comprising a second semiconductor material having a different lattice constant than said first semiconductor material and epitaxially aligned to said first end portion; and

a second stress-generating semiconductor portion in contact with a sidewall of said proximal portion of said second end portion and comprising said second semiconductor material and epitaxially aligned to said second end portion.

2. The semiconductor structure of claim 1, wherein said first stress-generating semiconductor portion is in contact with an entirety of a top surface of said distal portion of said first end portion and a sidewall surface of said first end portion, and said second stress-generating semiconductor portion is in contact with an entirety of a top surface of said distal portion of said second end portion and a sidewall surface of said second end portion.

3. The semiconductor structure of claim 1, further comprising a buried insulator layer comprising a dielectric material and having a planar top surface, wherein an entirety of a bottom surface of said fin-containing semiconductor portion laterally extending from a sidewall surface of said distal portion of said first end portion to a sidewall surface of said distal portion of said second end portion is in contact with said planar top surface.

4. The semiconductor structure of claim 1, further comprising a gate dielectric in contact with a lengthwise sidewall of said plurality of semiconductor fins.

5. The semiconductor structure of claim 4, further comprising a gate electrode overlying said plurality of semiconductor fins and in contact with said gate dielectric.

6. The semiconductor structure of claim 1, wherein an entire top surface of said first stress-generating semiconductor portion and an entire top surface of said second stress-generating semiconductor portion are within a same horizontal plane.

7. The semiconductor structure of claim 1, further comprising:

a first gate spacer portion contacting said first end portion and having a same thickness as a lateral extent of said proximal portion of said first end portion along a lengthwise direction of said plurality of semiconductor fins; and

a second gate spacer portion contacting said second end portion and having a same thickness as a lateral extent of said proximal portion of said second end portion along said lengthwise direction of said plurality of semiconductor fins.

8. A semiconductor structure comprising:

a fin-containing semiconductor portion comprising a first semiconductor material and including a plurality of semiconductor fins, a first end portion, and a second end portion, wherein each semiconductor fin among said plurality of semiconductor fins is laterally spaced from each other or one another along a widthwise direction, and a lengthwise end of each of said plurality of semiconductor fins is adjoined to said first end portion and another lengthwise end of each of said plurality of semiconductor fins is adjoined to said second end portion, wherein each of said first end portion and said second end portion includes a proximal portion having a same height as said plurality of semiconductor fins and a distal portion having a lesser height than said plurality of semiconductor fins;

a first stress-generating semiconductor portion in contact with a sidewall of said proximal portion of said first end portion and comprising a second semiconductor material having a different lattice constant than said first semiconductor material and epitaxially aligned to said first end portion;

a second stress-generating semiconductor portion in contact with a sidewall of said proximal portion of said second end portion and comprising said second semiconductor material and epitaxially aligned to said second end portion; and

a plurality of fin-defining mask structures overlying said plurality of semiconductor fins, said plurality of semiconductor fins has a same width as said plurality of fin-defining mask structures.

9. The semiconductor structure of claim 8, wherein said plurality of fin-defining mask structures comprises a dielectric material.

10. The semiconductor structure of claim 8, wherein said first stress-generating semiconductor portion is in contact with each of said plurality of fin-defining mask structures, and said second stress-generating semiconductor portion is in contact with each of said plurality of fin-defining mask structures.

11. A method of forming a semiconductor structure comprising:

forming a plurality of fin-defining mask structures over a semiconductor material layer comprising a first semiconductor material;

forming a disposable gate structure and a gate spacer over middle portions of said plurality of fin-defining mask structures;

recessing portions of said semiconductor material layer that are not covered by said disposable gate structure or by said gate spacer;

forming a first stress-generating semiconductor portion and a second stress-generating semiconductor portion comprising a second semiconductor material that is different from said first semiconductor material on said recessed portions of said semiconductor material layer;

removing said disposable gate structure to form a gate cavity; and

forming a plurality of semiconductor fins by transferring a pattern of said plurality of fin-defining mask structures within said gate cavity into said remaining portion of said semiconductor material layer.

12. The method of claim 11, wherein forming of said first stress-generating semiconductor material portion comprises depositing said second semiconductor material in epitaxial alignment with one of said recessed portions of said semiconductor material layer selective to dielectric surfaces, and said forming of said second stress-generating semiconductor material portion comprises depositing said second semiconductor material in epitaxial alignment with another of said recessed portions of said semiconductor material layer selective to said dielectric surfaces.

13. The method of claim 12, wherein said semiconductor material layer is provided as a top semiconductor layer of a semiconductor-on-insulator (SOI) layer including a buried insulator layer, and each of said recessed portions of said semiconductor material layer include a vertical sidewall that is vertically coincident with a sidewall of said gate spacer.

14. The method of claim 13, wherein each of said recessed portions has a planar recessed surface that is located below a plane of a topmost surface of said semiconductor material layer and above an interface between said semiconductor material layer and said buried insulator layer.

15. The method of claim 14, wherein said planar recessed surface overlies an entirety of one of said recessed portions.

16. The method of claim 14, wherein a first sidewall and a second sidewall are formed on said semiconductor material layer by said recessing of said portions of said, wherein said first stress-generating semiconductor portion is formed directly on an entirety of said first sidewall, and said second stress-generating semiconductor portion is formed directly on an entirety of said second sidewall.

17. The method of claim 11, wherein said forming of said gate spacer comprises:

depositing a conformal dielectric material layer on said disposable gate structure and over said plurality of fin-defining mask structures; and

etching vertical portions of said conformal dielectric material layer and portions of said plurality of fin-defining mask structures that are not covered by said disposable gate structure or by vertical portions of said conformal dielectric material layer.

18. The method of claim 17, wherein said conformal dielectric material layer and said fin-defining mask structures comprise a same dielectric material.

19. The method of claim 11, further comprising:

forming a gate dielectric directly on a lengthwise sidewall of said plurality of semiconductor fins; and

forming a gate electrode on said gate dielectric.

20. The method of claim 11, wherein said first semiconductor material is silicon, and said second semiconductor material is selected from undoped germanium, p-doped germanium, n-doped germanium, an undoped silicon germanium alloy, a p-doped silicon germanium alloy, an n-doped silicon germanium alloy, an undoped silicon carbon alloy, a p-doped silicon carbon alloy, and an n-doped silicon carbon alloy.