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BORDERLESS CONTACTS FOR METAL GATES THROUGH SELECTIVE CAP DEPOSITION

  • US 20130320414A1
  • Filed: 02/21/2013
  • Published: 12/05/2013
  • Est. Priority Date: 06/05/2012
  • Status: Abandoned Application
First Claim
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1. A semiconductor device comprising:

  • a gate structure present on a channel portion of a substrate, wherein the gate structure comprises a gate dielectric layer and at least one metal gate conductor;

    a source region and a drain region present on opposing sides of the channel portion of the substrate;

    a dielectric spacer adjacent to the gate structure;

    an etch stop layer on the entire exterior surface of the dielectric spacer, wherein an upper surface of the etch stop layer is coplanar with an upper surface of the gate structure;

    a metal oxide gate cap on the upper surface of the etch stop layer and the upper surface of the gate structure;

    contacts that extend through an intralevel dielectric layer into contact with at least one of the source region and the drain region.

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