Power MOSFET and Methods for Forming the Same

• US 20130320437A1
• Filed: 09/13/2012
• Published: 12/05/2013
• Est. Priority Date: 06/01/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ng, Chun-Wai, Chou, Hsueh-Liang, Su, Po-Chih, Liu, Ruey-Hsin
• Granted Patent: US 8,969,955 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A device includes a trench extending into a semiconductor region and having a first conductivity type, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer and having an edge portion overlapping the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion contacting the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type. A MOS-containing device is at a surface of the semiconductor region.

Claims

1. A device comprising:

a semiconductor region of a first conductivity type;

a trench extending into the semiconductor region;

a field plate in the trench, wherein the field plate is conductive;

a first dielectric layer separating a bottom and sidewalls of the field plate from the semiconductor region;

a main gate in the trench and overlapping the field plate;

a second dielectric layer between and separating the main gate and the field plate from each other;

a Doped Drain (DD) region of the first conductivity type under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region;

a body region comprising a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type; and

a Metal-Oxide-Semiconductor (MOS) containing device at a surface of the semiconductor region, wherein the MOS containing device is selected from the group consisting essentially of a High Voltage (HV) N-type MOS (HVNMOS) device, an HV P-type MOS (HVPMOS) device, a Low Voltage (LV) N-type MOS (LVNMOS) device, an LV P-type MOS (LVPMOS) device, and combinations thereof.

2. The device of claim 1, wherein the field plate and the main gate are comprised in a trench power MOS Field Effect Transistor (MOSFET), and wherein the trench power MOSFET further comprises:

a source region comprising first portions over the field plate and the main gate; and

a buried semiconductor layer of the first conductivity underlying the semiconductor region, wherein the buried semiconductor layer acts as a drain of the trench power MOSFET; and

a metal deep via penetrating through the semiconductor region to contact the buried semiconductor layer.

3. The device of claim 1, wherein the field plate and the main gate are comprised in a trench power Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), and wherein the trench power MOSFET further comprises:

a source region comprising first portions over the field plate and the main gate; and

a drain region underlying the semiconductor region.

4. The device of claim 1, wherein the MOS containing device comprises the HNMOS device comprising:

a Low Voltage Well (LVW) region of p-type;

a gate electrode over the LVW region, wherein the LVW region extends from a source side of the HVNMOS device to underlying the gate electrode; and

an n-type source region and an n-type drain region on opposite sides of, and adjacent to, the gate electrode, wherein the n-type source region is in the LVW region.

5. The device of claim 1, wherein the MOS containing device comprises the HVPMOS device comprising:

a lightly doped drain region in the semiconductor region, wherein the lightly doped drain region is of p-type;

a gate electrode over a portion of the lightly doped drain region; and

a source region and a drain region of p-type on opposite sides of, and adjacent to, the gate electrode, wherein the drain region is spaced apart from gate electrode by a portion of the lightly doped drain region.

6. The device of claim 1, wherein the MOS containing device comprises the LVNMOS device.

7. The device of claim 1, wherein the MOS containing device comprises the LVPMOS device.

8. The device of claim 1, wherein the DD region contacts a sidewall portion of the first dielectric layer, and wherein the DD region has a bottom surface higher than a bottom surface of the field plate.

9. The device of claim 1, wherein the second dielectric layer comprises:

a bottom surface contacting a top surface of the DD region; and

a top surface contacting a bottom surface of the main gate.

10. A device comprising:

a semiconductor region of a first conductivity type selected from the group consisting essentially of p-type and n-type;

a trench power Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) comprising;

a trench extending from a top surface of the semiconductor region into the semiconductor region;

a first dielectric layer lining a bottom and sidewalls of the trench;

a field plate comprising a bottom and sidewalls contacting the first dielectric layer, wherein the field plate is conductive;

a main gate in the trench and overlapping the field plate;

a second dielectric layer between and separating the main gate and the field plate from each other; and

a Doped Drain (DD) region of the first conductivity type, wherein the DD region comprising a top surface contacting the second dielectric layer, and a sidewall contacting the first dielectric layer, wherein the DD region has an impurity concentration greater than an impurity concentration of the semiconductor region; and

a lateral MOS device at a surface of the semiconductor region.

11. The device of claim 10, wherein the lateral MOS device comprises:

a doped region in the semiconductor region and of a second conductivity type opposite the first conductivity type;

a gate electrode, wherein the doped region extends from a source side of the MOS device to underlying the gate electrode; and

a source region and a drain region on opposite sides of, and adjacent to, the gate electrode, wherein the source region is in the doped region, and wherein the source region and the drain region are of the first conductivity type.

12. The device of claim 11 further comprising:

a high voltage well region of the first conductivity type underlying the doped region, the gate electrode, and the drain region, wherein the drain region is in the high voltage well region;

a deep well region of the second conductivity type underlying the high voltage well region; and

a buried well layer under the deep well region and of the first conductivity type.

13. The device of claim 10, wherein the lateral MOS device comprises:

a doped region in the semiconductor region and a second conductivity type opposite the first conductivity type;

a gate electrode, wherein the doped region extends from a drain side of the MOS device to underlying the gate electrode; and

a source region and a drain region on opposite sides of, and adjacent to, the gate electrode, wherein the drain region is in the doped region, and wherein the source region and the drain region are of the second conductivity type.

14. The device of claim 10, wherein the trench power MOSFET further comprises:

a buried semiconductor layer of the first conductivity underlying the semiconductor region, wherein the buried semiconductor layer acts as a drain of the trench power MOSFET; and

a metal deep via penetrating through the semiconductor region to contact the buried semiconductor layer.

15. The device of claim 14, wherein the drain region of the trench power MOSFET further comprises a metal plate underlying the semiconductor region.

16. A method comprising:

epitaxially growing an epitaxy semiconductor region of a first conductivity type;

forming a first trench in the epitaxy semiconductor region;

forming an implantation mask extending into the trench and covering edge portions of the trench;

performing a tilt implantation to form a Doped Drain (DD) region in the epitaxy semiconductor region, wherein the DD region comprises first portions overlapped by the implantation mask, and wherein the DD region is of a first conductivity type;

etching the epitaxy semiconductor region to extend the trench further down into the epitaxy semiconductor region, wherein the step of etching is performed using the implantation mask as an etching mask;

after the step of etching, forming a first dielectric layer lining a bottom and sidewalls of the trench;

forming a field plate in the trench and over the first dielectric layer, wherein the field plate comprises a bottom and sidewalls contacting the first dielectric layer;

forming a second dielectric layer over the field plate;

forming a main gate in the trench and over the second dielectric layer; and

forming a MOS device at a surface of the epitaxy semiconductor region.

17. The method of claim 16, wherein the step of forming the MOS device comprises:

implanting the epitaxy semiconductor region to form a doped well region of a second conductivity type opposite the first conductivity type;

forming a gate electrode to overlap a portion of the doped well region;

forming a source region in the doped well region; and

forming a drain region outside of the doped well region, wherein the source and the drain regions are of the first conductivity type.

18. The method of claim 16, wherein the step of forming the MOS device comprises:

implanting the epitaxy semiconductor region to form a doped well region of a second conductivity type opposite the first conductivity type;

forming a gate electrode to overlap a portion of the doped well region;

forming a source region outside the doped well region; and

forming a drain region in the doped well region, wherein the source and the drain regions are of the second conductivity type.

19. The method of claim 16 further comprising implanting a top portion of the epitaxy region to form a body region of a second conductivity type opposite the first conductivity type, wherein the body region comprises a portion level with a portion of the main gate, and wherein the body region joins the DD region.

20. The method of claim 16 further comprising:

forming a source region over the epitaxy semiconductor region; and

forming a drain region under the epitaxy semiconductor region, wherein the source region, the drain region, the DD region, the field plate, and the main gate form a power Metal-oxide-Semiconductor Field Effect Transistor (MOSFET).