Semiconductor Isolation Structure with Air Gaps in Deep Trenches
First Claim
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1. A device comprising:
- a semiconductor substrate;
a contact plug over the semiconductor substrate; and
an Inter-Layer Dielectric (ILD) layer comprising a portion over the semiconductor substrate, with the contact plug being disposed in the ILD layer, wherein an air gap is sealed by a portion of the ILD layer and the semiconductor substrate, wherein at least a portion of the air gap is lower than a top surface of the semiconductor substrate, and wherein the air gap forms a full air gap ring encircling a portion of the semiconductor substrate.
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Abstract
A device includes a semiconductor substrate, a contact plug over the semiconductor substrate, and an Inter-Layer Dielectric (ILD) layer over the semiconductor substrate, with the contact plug being disposed in the ILD. An air gap is sealed by a portion of the ILD and the semiconductor substrate. The air gap forms a full air gap ring encircling a portion of the semiconductor substrate.
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Citations
26 Claims
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1. A device comprising:
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a semiconductor substrate; a contact plug over the semiconductor substrate; and an Inter-Layer Dielectric (ILD) layer comprising a portion over the semiconductor substrate, with the contact plug being disposed in the ILD layer, wherein an air gap is sealed by a portion of the ILD layer and the semiconductor substrate, wherein at least a portion of the air gap is lower than a top surface of the semiconductor substrate, and wherein the air gap forms a full air gap ring encircling a portion of the semiconductor substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A device comprising:
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a semiconductor substrate; a trench extending from a top surface of the semiconductor substrate into the semiconductor substrate; a Metal-Oxide-Semiconductor (MOS) device at the top surface of the semiconductor substrate, wherein the MOS device comprises; a gate electrode over the semiconductor substrate; and a source/drain region adjacent the gate electrode and the trench; and an Inter-Layer Dielectric (ILD) layer comprising a portion over the gate electrode and the source/drain region, wherein the ILD layer further extends into the trench, and wherein the ILD layer seals an air gap in the trench. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15-20. -20. (canceled)
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21. A device comprising:
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a semiconductor substrate; a trench extending from a top surface of the semiconductor substrate into the semiconductor substrate; a Metal-Oxide-Semiconductor (MOS) device at the top surface of the semiconductor substrate; and an Inter-Layer Dielectric (ILD) layer comprising a portion over a gate electrode and a source/drain region of the MOS device, wherein the ILD layer further extends into the trench, the ILD layer seals an air gap in the trench, wherein at least a portion of the air gap is below the top surface of the semiconductor substrate. - View Dependent Claims (22, 23, 24, 25, 26)
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Specification