Semiconductor Isolation Structure with Air Gaps in Deep Trenches

• US 20130320459A1
• Filed: 06/01/2012
• Published: 12/05/2013
• Est. Priority Date: 06/01/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Shue, Hong-Seng, Yang, Tai-I, Wu, Wei-Ding, Chung, Ming-Tai, Yu, Shao-Chi
• Granted Patent: US 9,269,609 B2
• Time in Patent Office: Days
• US Class Current: 257/392
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 2221/1047 the air gaps being formed by pores in the dielectric
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps

Abstract

A device includes a semiconductor substrate, a contact plug over the semiconductor substrate, and an Inter-Layer Dielectric (ILD) layer over the semiconductor substrate, with the contact plug being disposed in the ILD. An air gap is sealed by a portion of the ILD and the semiconductor substrate. The air gap forms a full air gap ring encircling a portion of the semiconductor substrate.

Claims

1. A device comprising:

a semiconductor substrate;

a contact plug over the semiconductor substrate; and

an Inter-Layer Dielectric (ILD) layer comprising a portion over the semiconductor substrate, with the contact plug being disposed in the ILD layer, wherein an air gap is sealed by a portion of the ILD layer and the semiconductor substrate, wherein at least a portion of the air gap is lower than a top surface of the semiconductor substrate, and wherein the air gap forms a full air gap ring encircling a portion of the semiconductor substrate.

2. The device of claim 1 further comprising:

a Metal-Oxide-Semiconductor (MOS) device at a top surface of the semiconductor substrate, wherein the MOS device comprises;

a gate electrode over the semiconductor substrate; and

a source/drain region adjacent the gate electrode, wherein the ILD layer comprises a first portion extending over the gate electrode and the source/drain region, and a second portion extending into the semiconductor substrate, and wherein the air gap and the source/drain region are on opposite sides of the second portion of the ILD layer.

3. The device of claim 2 further comprising a source/drain silicide region over the source/drain region, wherein the ILD layer comprises a portion overlapping the source/drain silicide region.

4. The device of claim 2, wherein the first and the second portions of the ILD layer are continuously connected to a portion of the ILD layer in the semiconductor substrate and underlying the air gap to form a continuous ILD region.

5. The device of claim 1 further comprising an additional air gap in the semiconductor and forming an additional full air gap ring encircling a portion of the semiconductor substrate, wherein a side of the full air gap ring is parallel to a side of the additional full air gap ring.

6. The device of claim 5 further comprising a MOS device disposed at a surface of the portion of the semiconductor substrate.

7. The device of claim 6, wherein the MOS device is a high-voltage MOS device, and wherein the device further comprises:

a low-voltage MOS device at a top surface of the semiconductor substrate; and

a Shallow Trench Isolation (STI) region extending into the semiconductor substrate, wherein the STI region fon is a ring encircling the low-voltage MOS device, and wherein the high-voltage MOS device has a breakdown voltage higher than a breakdown voltage of the low-voltage MOS device.

8. A device comprising:

a semiconductor substrate;

a trench extending from a top surface of the semiconductor substrate into the semiconductor substrate;

a Metal-Oxide-Semiconductor (MOS) device at the top surface of the semiconductor substrate, wherein the MOS device comprises;

a gate electrode over the semiconductor substrate; and

a source/drain region adjacent the gate electrode and the trench; and

an Inter-Layer Dielectric (ILD) layer comprising a portion over the gate electrode and the source/drain region, wherein the ILD layer further extends into the trench, and wherein the ILD layer seals an air gap in the trench.

9. The device of claim 8, wherein in a top view of the MOS device, the air gap forms a full ring encircling the MOS device.

10. The device of claim 8, wherein substantially an entirety of the air gap is below the top surface of the semiconductor substrate.

11. The device of claim 8, wherein the ILD layer comprises a lower portion, and an upper portion over the lower portion, wherein the lower portion and the upper portion comprise different materials, and wherein the lower portion extends into the trench.

12. The device of claim 11 further comprising a shallow trench isolation region in the semiconductor substrate having a height, wherein the trench has a thickness ranging between about two times and about ten times the height.

13. The device of claim 8, wherein in a top view of the MOS device, the air gap forms a full ring encircling the MOS device.

14. The device of claim 13, wherein the MOS device is a high-voltage MOS device, and wherein the device further comprises:

a low-voltage MOS device at the top surface of the semiconductor substrate; and

a Shallow Trench Isolation (STI) region extending into the semiconductor substrate, wherein the STI region forms a ring encircling the low-voltage MOS device, and wherein the high-voltage MOS device has a breakdown voltage higher than a breakdown voltage of the low-voltage MOS device.

15-20. -20. (canceled)

21. A device comprising:

a semiconductor substrate;

a trench extending from a top surface of the semiconductor substrate into the semiconductor substrate;

a Metal-Oxide-Semiconductor (MOS) device at the top surface of the semiconductor substrate; and

an Inter-Layer Dielectric (ILD) layer comprising a portion over a gate electrode and a source/drain region of the MOS device, wherein the ILD layer further extends into the trench, the ILD layer seals an air gap in the trench, wherein at least a portion of the air gap is below the top surface of the semiconductor substrate.

22. The device of claim 21, wherein the top end of the air gap projects above the top surface of the semiconductor substrate.

23. The device of claim 21, wherein the top end of the air gap is disposed below the top surface of the semiconductor substrate.

24. The device of claim 21, wherein the air gap forms a full ring.

25. The device of claim 21, wherein a volume of the air gap is between about 0.3 to about 0.9 times a volume of the deep trench.

26. The device of claim 21, wherein a depth of the trench is between about 2 to about 10 times a height of a laterally adjacent shallow trench isolation region.