ON-CHIP RESISTOR

• US 20130320497A1
• Filed: 06/04/2013
• Published: 12/05/2013
• Est. Priority Date: 06/05/2012
• Status: Active Grant

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: ZHANG, Guowei, VERMA, Purakh Raj, KHON, Cho
• Granted Patent: US 9,105,502 B2
• Time in Patent Office: Days
• US Class Current: 257/538
• CPC Class Codes: H01L 27/016 Thin-film circuits
• CPC Class Codes: H01L 27/101 including resistors or capacitors only

Abstract

An integrated circuit (IC) is disclosed. The IC includes a substrate with a resistor region and a resistor body disposed on the resistor region. A plurality of first resistor contact strips and a plurality of second resistor contact strips are disposed on the resistor body along a first direction. Two adjacent first and second resistor contact strips are separated by a respective one of contact strip spaces. The IC includes a plurality of first terminals and a plurality of second terminals. Each of the first terminals is coupled to a respective one of the first resistor contact strips while each of the second terminals is coupled to a respective one of the second resistor contact strips. A set of the first terminal and the second terminal forms first and second terminals of an on-chip resistor.

Claims

1. An integrated circuit (IC), comprising:

a substrate with a resistor region;

a resistor body disposed on the resistor region;

a plurality of first resistor contact strips and a plurality of second resistor contact strips disposed on the resistor body along a first direction, two adjacent first and second resistor contact strips being separated by a respective one of contact strip spaces;

a plurality of first terminals, each of the first terminals coupled to a respective one of the first resistor contact strips; and

a plurality of second terminals, each of the second terminals coupled to a respective one of the second resistor contact strips,

wherein a set of the first terminal and the second terminal forms a first and a second terminals of an on-chip resistor.

2. The IC of claim 1, wherein the first and the second resistor contact strips comprise metal contact strips and silicide contact strips.

3. The IC of claim 2, wherein the silicide contact strips comprise nickel silicide, titanium silicide, cobalt silicide, tungsten silicide, or platinum silicide.

4. The IC of claim 1, wherein the resistor body comprises polysilicon, Ta, or TaN.

5. The IC of claim 4, wherein the resistor body comprises heavily doped polysilicon.

6. The IC of claim 5, wherein the resistor body comprises heavily p-doped polysilicon.

7. The IC of claim 1, wherein the resistor region comprises an isolation region on which the resistor body is disposed.

8. The IC of claim 7, wherein the isolation region comprises a trench isolation region.

9. The IC of claim 1, wherein:

each of the first terminals comprises

a plurality of first conductive lines disposed above a respective one of the first resistor contact strips,

a plurality of first contacts, the first contacts coupled the respective one of the first contact strips to corresponding first conductive lines; and

each of the second terminals comprises

a plurality of second conductive lines disposed above a respective one of the second resistor contact strips,

a plurality of second contacts, the second contacts coupled the respective one of the second contact strips to corresponding second conductive lines.

10. The IC of claim 9, further comprising a first conductive terminal plate having a first face and a second conductive terminal plate having a second face facing the first face, wherein:

the first conductive terminal plate is coupled to the first conductive lines; and

the second conductive terminal plate is coupled to the second conductive lines.

11. The IC of claim 10, wherein:

the first and second conductive lines are disposed on a first metal layer of the IC; and

the first and second conductive terminal plates are disposed on a second metal layer of the IC.

12. The IC of claim 11, wherein the first metal layer is a lowest metal layer (M₁) of the IC and the second metal layer is a highest metal layer (Mx) of the IC, and x is an integer greater than 1.

13. The IC of claim 12, wherein one or more intermediate metal layers are disposed between M₁ and M_X, the one or more intermediate metal layers having a same pattern as that of the M_X.

14. The IC of claim 1, wherein a plurality of on-chip resistors are coupled in parallel.

15. The IC of claim 1, wherein the on-chip resistor is disposed below a bond pad of the IC.

16. The IC of claim 10, wherein the first face of the first terminal plate and the second face of the second terminal plate are slanted in a current flow direction of the resistor.

17. An integrated circuit (IC), comprising:

a substrate with a resistor region;

a resistor body disposed on the resistor region;

a plurality of first terminals coupled to the resistor body; and

a plurality of second terminals coupled to the resistor body,

wherein a set of the first terminal and the second terminal forms a first and a second terminals of an on-chip resistor.

18. The IC of claim 17, wherein the resistor body is a conductive metal comprising Ta, or TaN.

19. The IC of claim 17, wherein the resistor region comprises an isolation region on which the resistor body is disposed.

20. The IC of claim 19, wherein the isolation region comprises a trench isolation region.