PROGRAMMABLE LOGIC DEVICE

• US 20130321025A1
• Filed: 05/24/2013
• Published: 12/05/2013
• Est. Priority Date: 05/30/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurokawa, Yoshiyuki, Ikeda, Takayuki
• Granted Patent: US 9,007,093 B2
• Time in Patent Office: Days
• US Class Current: 326/41
• CPC Class Codes: H03K 19/0944 using MOSFET or insulated gate field-effect transistors, i.e. IGFETH03K19/096 takes precedence
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17772 for powering on or off

Abstract

A PLD in which a configuration memory is formed using a nonvolatile memory with a small number of transistors and in which the area of a region where the configuration memory is disposed is reduced is provided. Further, a PLD that is easily capable of dynamic reconfiguration and has a short startup time is provided. A programmable logic device including a memory element, a selector, and an output portion is provided. The memory element includes a transistor in which a channel is formed in an oxide semiconductor film, and a storage capacitor and an inverter which are connected to one of a source and a drain of the transistor. The inverter is connected to the selector. The selector is connected to the output portion.

Claims

1. A programmable logic device comprising:

a first memory element;

a selector; and

an output portion,

wherein the first memory element comprises;

a first transistor comprising an oxide semiconductor layer, wherein a channel is formed in the oxide semiconductor layer;

a first storage capacitor; and

a first inverter,

wherein one of a source and a drain of the first transistor is electrically connected to the first storage capacitor and an input portion of the first inverter,

wherein an output portion of the first inverter is electrically connected to the selector, and

wherein the selector is electrically connected to the output portion.

2. The programmable logic device according to claim 1,

wherein a gate of the first transistor is electrically connected to a writing control line, and

wherein the other of the source and the drain of the first transistor is electrically connected to a writing data line.

3. The programmable logic device according to claim 1,

wherein the selector comprises a plurality of 1-bit selectors each comprising an input terminal, a second inverter and a second transistor, and

wherein conduction between the first memory element and the output portion depends on a conduction state of the second transistor, the conduction state being determined by a signal input from the input terminal.

4. The programmable logic device according to claim 1 further comprising:

a second transistor,

wherein the output portion of the first inverter is electrically connected to the selector through the second transistor, and

wherein a gate of the second transistor is electrically connected to a first reading control line.

5. The programmable logic device according to claim 1 further comprising:

a second memory element,

wherein the second memory element comprises;

a second transistor comprising an oxide semiconductor layer, wherein a channel is formed in the oxide semiconductor layer;

a second storage capacitor;

a second inverter; and

a third transistor,

wherein one of a source and a drain of the second transistor is electrically connected to the second storage capacitor and an input portion of the second inverter,

wherein an output portion of the second inverter is electrically connected to one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to the selector, and

wherein a gate of the third transistor is electrically connected to a second reading control line.

6. A programmable logic device comprising:

a first memory element;

a selector;

a precharge circuit; and

an output portion,

wherein the first memory element comprises;

a first transistor comprising an oxide semiconductor layer, wherein a channel is formed in the oxide semiconductor layer; and

a second transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the second transistor is electrically connected to the selector, and

wherein the selector is electrically connected to the precharge circuit and the output portion.

7. The programmable logic device according to claim 6 further comprising a latch circuit between the selector and the output portion.

8. The programmable logic device according to claim 6,

wherein a gate of the first transistor is electrically connected to a writing control line, and

wherein the other of the source and the drain of the first transistor is electrically connected to a writing data line.

9. The programmable logic device according to claim 6 further comprising:

a storage capacitor electrically connected to a node where the one of the source and the drain of the first transistor and the gate of the second transistor are electrically connected to each other,

wherein the node is electrically connected to a reading control line through the storage capacitor.

10. The programmable logic device according to claim 6,

wherein the selector comprises a plurality of 1-bit selectors each comprising an input terminal, an inverter and a third transistor, and

wherein conduction between the first memory element and the output portion depends on a conduction state of the third transistor, the conduction state being determined by a signal input from the input terminal.

11. The programmable logic device according to claim 6 further comprising:

a third transistor,

wherein the one of the source and the drain of the second transistor is electrically connected to the selector through the third transistor, and

wherein a gate of the third transistor is electrically connected to a first reading control line.

12. The programmable logic device according to claim 6 further comprising:

a second memory element,

wherein the second memory element comprises;

a third transistor comprising an oxide semiconductor layer, wherein a channel is formed in the oxide semiconductor layer;

a fourth transistor; and

a fifth transistor,

wherein one of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor, and

wherein the other of the source and the drain of the fifth transistor is electrically connected to the selector.

13. A programmable logic device comprising:

a first logic element and a second logic element; and

a selector,

wherein each of the first logic element and the second logic element comprises;

a plurality of memory elements, wherein each of the plurality of memory elements comprises;

a first transistor comprising an oxide semiconductor layer, wherein a channel is formed in the oxide semiconductor layer;

a node configured to store a data; and

a second transistor,

wherein the node is an electrically floating state when the first transistor is turned off,

wherein conduction between a source and a drain of the second transistor depends on the data stored in the node,

wherein one of the source and the drain of the second transistor is electrically connected to the selector,

wherein the selector is electrically connected to each of the plurality of memory elements, and

wherein a first predetermined logic circuit and a second predetermined logic circuit are respectively set in the first logic element and the second logic element depending on a conduction state of the second transistor and selection of any of the plurality of memory elements by the selector.