THIN SUBSTRATE ELECTROSTATIC CHUCK SYSTEM AND METHOD

• US 20130321973A1
• Filed: 06/01/2012
• Published: 12/05/2013
• Est. Priority Date: 06/01/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Wiltsche, Ewald, Zupan, Peter
• Granted Patent: US 9,030,797 B2
• Time in Patent Office: Days
• US Class Current: 361/234
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/67103 mainly by conduction
• CPC Class Codes: H01L 21/67253 Process monitoring, e.g. flow or thickness monitoring
• CPC Class Codes: H01L 21/6831 using electrostatic chucks
• CPC Class Codes: H01L 21/6833 Details of electrostatic chucks
• CPC Class Codes: H01L 21/68764 characterised by a movable susceptor, stage or support, others than those only rotating on their own vertical axis, e.g. susceptors on a rotating caroussel
• CPC Class Codes: H02N 13/00 Clutches or holding devices using electrostatic attraction, e.g. using Johnson-Rahbek effect
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing

Abstract

In various aspects of the disclosure, a semiconductor substrate processing system may include an electrostatic chuck for holding a semiconductor substrate attached to an electrically insulating carrier; and an AC power supply electrically coupled to the electrostatic chuck.

Claims

1. A processing system, comprising:

an electrostatic chuck for holding a semiconductor substrate attached to an electrically insulating carrier, wherein the electrically insulating carrier is disposed between the electrostatic chuck and the semiconductor substrate;

an AC power supply electrically coupled to the electrostatic chuck;

wherein the supplied voltage is dependent on at least one property of the electrically insulating carrier.

2. The system of claim 1, wherein the AC power supply provides a voltage of at least 500 V peak to peak.

3. The system of claim 1, wherein the at least one property of the electrically insulating carrier comprises thickness of the electrically insulating carrier.

4. The system of claim 3, wherein the thickness comprises at least 0.2 mm.

5. The system of claim 1, wherein the at least one property of the electrically insulating carrier comprises the material used to form the electrically insulating carrier.

6. The system of claim 1, wherein the supplied voltage is further dependent on the weight of the semiconductor substrate and electrically insulating carrier.

7. The system of claim 1, further comprising a processing tool.

8. The system of claim 7, wherein the processing tool is an implant device.

9. The system of claim 1, wherein the AC power supply is a 6-phase high voltage AC power supply.

10. The system of claim 1, wherein the supplied voltage is at least 3 kV peak to peak.

11. A processing system, comprising:

an electrostatic chuck for holding a semiconductor substrate attached to an electrically insulating carrier, wherein the electrically insulating carrier is disposed between the electrostatic chuck and the semiconductor substrate;

an AC power supply electrically coupled to the electrostatic chuck wherein the AC power supply provides a voltage of at least 500 V peak to peak.

12. The processing system of claim 11, wherein the supplied voltage is at least 1 kV peak to peak.

13. The system of claim 11, wherein the supplied voltage is dependent on a thickness of the electrically insulating carrier.

14. The system of claim 11, wherein a thickness of the semiconductor substrate is less than or equal to 200 μ

m.

15. The system of claim 11, wherein a thickness of the semiconductor substrate is less than or equal to 100 μ

m.

16. The system of claim 11, wherein the supplied voltage is dependent on a material used to form the electrically insulating carrier.

17. The system of claim 13, wherein the supplied voltage is further dependent on the weight of the semiconductor substrate and electrically insulating carrier.

18. The system of claim 11, further comprising a processing tool.

19. The system of claim 18, wherein the processing tool is an implant device.

20. The system of claim 11, wherein the AC power supply is a 6-phase high voltage AC power supply.

21. The system of claim 11, wherein the supplied voltage is at least 3 kV peak to peak.

22. A method of manufacturing a device, the method comprising:

providing a semiconductor substrate;

attaching the semiconductor substrate to an electrically insulating carrier;

supporting the semiconductor substrate and electrically insulating carrier with an electrostatic chuck, the electrically insulating carrier being disposed between the electrostatic chuck and the semiconductor substrate;

wherein a voltage supplied to the electrostatic chuck is related to at least one property of the electrically insulating carrier.

23. The method of claim 22, wherein attaching the semiconductor substrate to the electrically insulating carrier comprises attaching the semiconductor substrate such that a front side of the semiconductor substrate faces the electrically insulating carrier.

24. The method of claim 22, wherein the at least one property is a thickness of the electrically insulating carrier.

25. The method of claim 22, wherein the at least one property is the material used to form the electrically insulating carrier.

26. The method of claim 22, wherein the voltage supplied to the electrostatic chuck is a high voltage.

27. The method of claim 26, wherein the high voltage is at least 500 V peak to peak.

28. The method of claim 26, wherein the high voltage ranges from 6-8 kV peak to peak.

29. The method of claim 22, wherein the electrically insulating carrier further comprises a conductive layer.

30. The method of claim 29, wherein the conductive layer is optically transmissive.

31. The method of claim 22, wherein the semiconductor substrate is a 300 mm substrate.

32. The method of claim 22, further comprising implanting the substrate.

33. The method of claim 32, wherein the implanting is done according to a Quad implant process.

34. The method of claim 32, wherein the implant process is a backside implant process.