VARIABLE RESISTANCE MEMORY DEVICE AND DATA STORAGE DEVICE INCLUDING THE SAME

• US 20130322155A1
• Filed: 08/21/2012
• Published: 12/05/2013
• Est. Priority Date: 05/31/2012
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: AHN, Chang Yong, EM, Ho Seok
• Granted Patent: US 8,848,420 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods

Abstract

A variable resistance memory device includes memory cells arranged at a region where word lines and bit lines cross each other, control logic configured to generate a command flag indicative of a program operation mode in response to a program command provided from an external device and configured to control the program operation of the memory cells based on the command flag and a write driver configured to be activated in response to the flag command and configured to supply a program current to the memory cells.

Claims

1. A variable resistance memory device, comprising:

memory cells arranged at a region where word lines and bit lines cross each other;

control logic configured to generate a command flag indicative of a program operation mode in response to a program command provided from an external device and configured to control a program operation of the memory cells based on the command flag; and

a write driver configured to be activated in response to the flag command and configured to supply a program current to the memory cells.

2. The variable resistance memory device according to claim 1, further comprising a register configured to temporarily store the program command, an address for selecting the memory cells, and data to be programmed into the memory cells.

3. The variable resistance memory device according to claim 2, wherein the control logic generates the command flag generally while the address is stored in the register is decoded and provides the generated command flag to the write driver.

4. The variable resistance memory device according to claim 1, wherein the control logic performs any one of an erase operation, a single program operation, a buffer program operation, a single overwrite program operation, and a buffer overwrite program operation based on the command flag.

5. The variable resistance memory device according to claim 4, wherein data of an erase state is programmed in all the memory cells through the erase operation.

6. The variable resistance memory device according to claim 4, wherein remaining data other than data of an erase state, from among data provided from the external device, is programmed into the memory cells through the single program operation.

7. The variable resistance memory device according to claim 4, wherein remaining data other than data of an erase state, from among data provided from the external device, is sequentially programmed into the memory cells from a start address to an end address of the memory cells through the buffer program operation.

8. The variable resistance memory device according to claim 4, wherein data provided from the external device is programmed into the memory cells through the single overwrite program operation.

9. The variable resistance memory device according to claim 4, wherein data provided from the external device is sequentially programmed into the memory cells from a start address to an end address of the memory cells through the buffer overwrite program operation.

10. The variable resistance memory device according to claim 1, wherein each of the memory cells comprises:

a memory element configured to have one end connected to the bit line and made of phase change materials; and

a selecting element configured to select the memory element.

11. The variable resistance memory device according to claim 10, wherein the selecting element comprises a diode connected between an other end of the memory element and the word line.

12. A data storage device, comprising:

a variable resistance memory device; and

a controller configured to control the variable resistance memory device,

wherein the variable resistance memory device comprises;

memory cells arranged at a region where word lines and bit lines cross each other;

control logic configured to generate a command flag indicative of a program operation mode in response to a program command provided from the controller and configured to control a program operation of the memory cells based on the command flag; and

a write driver configured to be activated in response to the flag command and configured to supply a program current to the memory cells.

13. The data storage device according to claim 12, wherein the variable resistance memory device further comprises a register configured to temporarily store the program command, an address for selecting the memory cells, and data to be programmed into the memory cells.

14. The data storage device according to claim 13, wherein the control logic generates the command flag generally while the address is stored in the register is decoded and provides the generated command flag to the write driver.

15. The data storage device according to claim 12, wherein the control logic performs any one of an erase operation, a single program operation, a buffer program operation, a single overwrite program operation, and a buffer overwrite program operation based on the command flag.

16. The data storage device according to claim 12, wherein each of the memory cells comprises:

a memory element configured to have one end connected to the bit line and made of phase change materials; and

a selecting element configured to select the memory element.

17. The data storage device according to claim 16, wherein the selecting element comprises a diode connected between an other end of the memory element and the word line.

18. The data storage device according to claim 16, wherein the phase change materials comprise a mixture of germanium, antimony, and tellurium.

19. The data storage device according to claim 12, wherein the variable resistance memory device and the controller are formed of a memory card.

20. The data storage device according to claim 12, wherein the variable resistance memory device and the controller are formed of a solid state drive.