PROGRAMMING OF GATED PHASE-CHANGE MEMORY CELLS

• US 20130322165A1
• Filed: 05/22/2013
• Published: 12/05/2013
• Est. Priority Date: 05/31/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Krebs, Daniel
• Granted Patent: US 9,293,198 B2
• Time in Patent Office: Days
• US Class Current: 365/163
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0009 RRAM elements whose operation depends upon chemical change
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0071 Write using write potential applied to access device gate
• CPC Class Codes: G11C 2013/0076 Write operation performed depending on read result
• CPC Class Codes: G11C 2213/53 Structure wherein the resistive material being in a transistor, e.g. gate
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/253 having three or more electrodes, e.g. transistor-like devices
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices

Abstract

A method for programming gated phase-change memory cells, each with a gate, source and drain, having s≧2 programmable cell-states including an amorphous RESET state and at least one crystalline state includes applying a programming signal between the source and drain of a memory cell to program that cell to a desired cell-state; and when programming the cell from a crystalline state to the RESET state, applying a bias voltage to the gate of the cell to increase the cell resistance.

Claims

1. A method for programming gated phase-change memory cells, each with a gate, source and drain, having s≧

2 programmable cell-states including an amorphous RESET state and at least one crystalline state, the method comprising;

applying a programming signal between the source and drain of a memory cell to program that cell to a desired cell-state; and

when programming the cell from a crystalline state to the RESET state, applying a bias voltage to the gate of the cell to increase the cell resistance.

2. The method of claim 1, further comprising:

reading the memory cell before programming to obtain an indication of cell-state; and

when programming the cell to the RESET state, applying the bias voltage only if a crystalline cell-state is indicated on reading.

3. The method of claim 1, wherein the bias voltage level is set to increase the cell resistance to a value at or near a predetermined maximum value for the crystalline state.

4. The method of claim 1, wherein the Fermi level for a cell in a crystalline state is in or near the conduction band, and wherein the bias voltage polarity is set to move the Fermi level towards the valence band on applying the bias voltage.

5. The method of claim 1, wherein the Fermi level for a cell in a crystalline state is in or near the valence band, and wherein the bias voltage polarity is set to move the Fermi level towards the conduction band on applying the bias voltage.

6. The method of claim 1, wherein, on programming the cell to a crystalline state, applying zero bias voltage to the gate of that cell.

7. The method of claim 1, further comprising on programming a cell to a crystalline state, applying a bias voltage for the crystalline state to the gate of the cell to program the crystalline state on application of the programming signal.

8. The method of claim 1, wherein each memory cell is connected to a respective access device for controlling access to the cell for programming, the method including accessing a memory cell via the access device when applying a programming signal to program the cell.

9. The method of claim 1, wherein s=2.

10. The method of claim 1, wherein s>

2.

11. A method for reading and writing data in gated phase-change memory cells, each with a gate, source and drain, having s≧

2 programmable cell-states including an amorphous RESET state and at least one crystalline state, the method comprising;

writing data in using the method of claim 1; and

reading data in memory cells by applying a read signal between the source and drain of each cell with zero bias voltage applied to the gate of the cell, and making a read measurement to obtain an indication of cell-state.

12-20. -20. (canceled)