PROGRAMMING OF GATED PHASE-CHANGE MEMORY CELLS
First Claim
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1. A method for programming gated phase-change memory cells, each with a gate, source and drain, having s≧
- 2 programmable cell-states including an amorphous RESET state and at least one crystalline state, the method comprising;
applying a programming signal between the source and drain of a memory cell to program that cell to a desired cell-state; and
when programming the cell from a crystalline state to the RESET state, applying a bias voltage to the gate of the cell to increase the cell resistance.
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Abstract
A method for programming gated phase-change memory cells, each with a gate, source and drain, having s≧2 programmable cell-states including an amorphous RESET state and at least one crystalline state includes applying a programming signal between the source and drain of a memory cell to program that cell to a desired cell-state; and when programming the cell from a crystalline state to the RESET state, applying a bias voltage to the gate of the cell to increase the cell resistance.
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Citations
12 Claims
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1. A method for programming gated phase-change memory cells, each with a gate, source and drain, having s≧
- 2 programmable cell-states including an amorphous RESET state and at least one crystalline state, the method comprising;
applying a programming signal between the source and drain of a memory cell to program that cell to a desired cell-state; and when programming the cell from a crystalline state to the RESET state, applying a bias voltage to the gate of the cell to increase the cell resistance. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
- 2 programmable cell-states including an amorphous RESET state and at least one crystalline state, the method comprising;
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12-20. -20. (canceled)
Specification