MULTI-LEVEL CELL (MLC) UPDATE WITH PROTECTED MODE CAPABILITY

• US 20130322169A1
• Filed: 05/31/2012
• Published: 12/05/2013
• Est. Priority Date: 05/31/2012
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Goss, Ryan James, Gaertner, Mark Allen, Seekins, David Scott
• Granted Patent: US 8,923,045 B2
• Time in Patent Office: Days
• US Class Current: 365/185.02
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G11C 11/34 using semiconductor devices
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells

Abstract

Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a first block of data is written to a group of memory cells at a first memory location in single-level cell (SLC) mode. The first block of data is copied from the first memory location to a group of memory cells at a second memory location to provide a backup copy of the first block of data during a protected mode of operation. A second block of data is subsequently overwritten to the group of memory cells at the first memory location so that the first memory location stores both the first and second blocks of data in multi-level cell (MLC) mode.

Claims

1. A method comprising:

writing a first block of data to a group of memory cells at a first memory location in single-level cell (SLC) mode;

copying the first block of data to a group of memory cells at a second memory location to provide a backup copy of the first block of data responsive to initiation of a protected mode of operation; and

overwriting a second block of data to the group of memory cells at the first memory location so that the first memory location stores both the first and second blocks of data in multi-level cell (MLC) mode.

2. The method of claim 1, in which the copying step is carried out responsive to an MLC update manager which initiates the protected mode of operation in response to a detected anomalous power condition.

3. The method of claim 1, further comprising detecting a variable parameter associated with the first memory location, and initiating the protected mode of operation responsive to the detected variable parameter.

4. The method of claim 1, further comprising subsequently performing a read verify operation upon the first memory location in an attempt to successfully retrieve the first and second blocks of data therefrom.

5. The method of claim 4, further comprising storing the first and second blocks of data to a group of memory cells at a third memory location responsive to the unsuccessful retrieval of the first and second blocks of data during the read verify operation.

6. The method of claim 4, in which the read verify operation comprises retrieving the backup copy of the first set of data from the second memory location and comparing said retrieved backup copy to a copy of the first set of data retrieved from the first memory location.

7. The method of claim 1, in which the respective groups of memory cells in the first and second memory locations comprise flash memory cells in a flash memory array.

8. The method of claim 1, in which the first memory location is a row of flash memory cells in a first erasure block and the second memory location is a row of flash memory cells in a second erasure block.

9. The method of claim 1, in which the second memory location stores the backup copy of the first block of data in MLC mode.

10. The method of claim 1, further comprising searching for an existing backup copy of the first set of data in a non-volatile memory array which incorporates the first and second memory locations as portions of said array, and performing the copying step responsive to a determination that said existing backup copy is not present in the array.

17. The apparatus of claim 1, in which the control circuit is further adapted to perform a read verify operation upon the first memory location in an attempt to successfully retrieve the first and second blocks of data therefrom, and to store the first and second blocks of data to a group of memory cells at a third memory location in the array responsive to the unsuccessful retrieval of the first and second blocks of data during the read verify operation.

11. An apparatus comprising a non-volatile memory array formed of memory cells, and a control circuit adapted to write a first block of data to a group of memory cells at a first memory location in the array in single-level cell (SLC) mode, and responsive to receipt of a second block of data for storage to the array and an initiated protected mode of operation, to copy the first block of data to a group of memory cells at a second memory location in the array to provide a backup copy of the first block of data, and to overwrite a second block of data to the group of memory cells at the first memory location in multi-level cell (MLC) mode so that each memory cell at the first memory location stores at least one bit from each of the first and second blocks of data.

12. The apparatus of claim 11, further comprising an MLC update manager which operates to initiate the protected mode of operation responsive to a detected anomalous power condition.

13. The apparatus of claim 11, in which the control circuit detects a variable parameter associated with the first memory location and stores the backup copy to the second memory location responsive to the detected variable parameter.

14. The apparatus of claim 13, in which the detected variable parameter is at least a selected one of a data aging value, a total accumulated read count, a total number of write/erasure cycles, an error rate or a read disturb value associated with the first memory location.

15. The apparatus of claim 11, in which the memory array is characterized as a flash memory array, the first memory location is a selected row of flash memory cells interconnected to a common word line in a first erasure block, and the second memory location is a selected row of flash memory cells interconnected to a common word line in a different, second erasure block.

16. The apparatus of claim 11, further comprising a power monitoring circuit which monitors a power level utilized by the apparatus, the control circuit generating the backup copy responsive to a detected anomalous condition associated with the monitored power level.

18. An apparatus comprising:

a memory module comprising an array of solid-state memory cells each having an associated address;

a multi-level cell (MLC) update manager which initiates a protected mode of operation; and

a control module which operates during said protected mode of operation to write a first block of data to the memory cells at a first memory location in the array in single-level cell (SLC) mode, to copy the first block of data from the first memory location to the memory cells at a second memory location in the array, and to overwrite the memory cells at the first memory location with the second block of data so that the first memory location stores both the first and second blocks of data in MLC mode with each memory cell in the first memory location storing at least one bit from each of the first and second blocks of data.

19. The apparatus of claim 18 further comprising a power monitoring circuit adapted to monitor a power source, wherein the MLC update manager initiates the protected mode of operation responsive to a detected anomalous power condition by the power monitoring circuit.

20. The apparatus of claim 18, in which the array is characterized as a flash memory array, the first memory location comprises a row of flash memory cells in a first erasure block of the array, the second memory location comprises a row of flash memory cells in a second erasure block of the array, and the copy of the first block of data in the second memory location is overwritten onto an existing set of copied data so that the second memory location stores data in MLC mode.