SEMICONDUCTOR DEVICE WITH IMPROVED ON-RESISTANCE

• US 20130323897A1
• Filed: 08/06/2013
• Published: 12/05/2013
• Est. Priority Date: 12/09/2009
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Mauder, Anton, Berger, Rudolf, Hirler, Franz, Siemieniec, Ralf, Schulze, Hans-Joachim
• Granted Patent: US 8,741,736 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a source, a drain, and a gate configured to selectively enable a current to pass between the source and the drain. The semiconductor device includes a drift zone between the source and the drain and a first field plate adjacent the drift zone. The semiconductor device includes a dielectric layer electrically isolating the first field plate from the drift zone and charges within the dielectric layer close to an interface of the dielectric layer adjacent the drift zone.

Claims

1. A method for manufacturing a semiconductor device, the method comprising:

etching a trench into a doped semiconductor substrate including a drift zone and a drain region;

forming a first dielectric layer over the substrate;

providing positive charges over the first dielectric layer;

depositing a second dielectric layer over the positive charges;

depositing a hard mask material or conductive material in the trench;

recess etching the hard mask material or the conductive material to expose portions of the second dielectric layer within the trench;

etching the second dielectric layer, the positive charges, and the first dielectric layer to expose the sidewalls of the trench above the hard mask or the conductive material; and

forming a third dielectric layer over the hard mask or conductive material layer and the exposed sidewalls of the trench.

2. The method of claim 1, wherein etching the second dielectric layer, the positive charges, and the first dielectric layer comprises etching the second dielectric layer, the positive charges, and the first dielectric layer to expose the sidewalls of the trench above the hard mask or the conductive material and to form a slope from the second dielectric layer adjacent the hard mask;

the method further comprising;

removing the hard mask;

depositing a conductive material layer at least over the second dielectric layer; and

recess etching the conductive material layer to expose portions of the sidewalls of the trench to provide a tapered field plate.

3. The method of claim 1, further comprising:

forming a gate and a source region in the substrate.

4. The method of claim 1, further comprising:

damaging the second dielectric layer such that the second dielectric layer has a faster etch rate than the first dielectric layer.

5. The method of claim 1, wherein depositing the second dielectric layer comprises depositing a second dielectric layer having a faster etch rate than the first dielectric layer.

6. The method of claim 1, wherein etching the trench into the doped semiconductor substrate comprises etching a trench through a field stop region between the drift zone and the drain region of the doped semiconductor substrate.

7. A method for manufacturing a semiconductor device, the method comprising:

etching a trench into a doped semiconductor substrate including a drift zone and a drain region;

forming a first dielectric layer over the substrate;

providing positive charges over the first dielectric layer;

depositing an etch stop material layer over the positive charges;

depositing a silicon layer over the etch stop material layer;

oxidizing a portion of the silicon layer;

depositing a hard mask material in the trench;

recess etching the hard mask material to expose portions of the oxidized silicon layer;

etching the oxidized silicon layer and portions of the silicon layer to form a slope from the silicon layer on the sidewalls of the trench adjacent the hard mask;

removing the hard mask;

oxidizing the sloped silicon layer;

depositing a conductive material layer over the oxidized sloped silicon layer;

recess etching the conductive material layer to expose portions of the sidewalls of the trench to provide a tapered field plate; and

forming a third dielectric layer over the conductive material layer and the exposed sidewalls of the trench.

8. The method of claim 7, wherein etching the oxidized silicon layer and portions of the silicon layer to form a slope from the silicon layer comprises etching using an isotropic oxide etch.

9. The method of claim 7, wherein forming the first dielectric layer over the substrate comprises thermally oxidizing the substrate.

10. The method of claim 7, further comprising:

forming a gate and a source region in the substrate.

11. The method of claim 7, wherein etching the trench into the doped semiconductor substrate comprises etching a trench through a field stop region between the drift zone and the drain region of the doped semiconductor substrate.

12. The method of claim 7, wherein providing the positive charges comprising depositing an electropositive material over the first dielectric layer.