USAGE OF A FLAG BIT TO SUPPRESS DATA TRANSFER IN A MASS STORAGE SYSTEM HAVING NON-VOLATILE MEMORY

• US 20130326113A1
• Filed: 05/29/2012
• Published: 12/05/2013
• Est. Priority Date: 05/29/2012
• Status: Abandoned Application

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Wakrat, Nir Jacob, Vogan, Andrew W.
• Application Number:
  US13/482,204
• Publication Number:
  US 20130326113A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/6024 History based prefetching

Abstract

Systems and methods are disclosed for usage of a flag bit to suppress data transfer in a mass storage system having non-volatile memory (“NVM”). In some embodiments, a host of the system can issue queue-able trim commands by dispatching non-data transfer write commands to the NVM. In some embodiments, the host can track the read behavior of a particular application over a period of time. As a result, the host can maintain heuristics of logical sectors that are most frequently read together. The host can then notify the NVM to pre-fetch data that the application will most likely request at some point in the future. These notifications can take the form of non-data transfer read commands. Each non-data transfer read commands can include a flag bit that is set to indicate that no data transfer is desired.

Claims

1. A method for performing non-data transfer access commands, the method comprising:

receiving information from a non-volatile memory (“

NVM”

) indicating that the NVM supports a flag bit command format;

saving access commands in a queue stored in volatile memory, wherein at least a subset of the access commands are non-data transfer access commands, and wherein each non-data transfer access command comprises a flag bit that is set to indicate one of lack of data association and that no data transfer is desired; and

dispatching each of the access commands in the queue, wherein dispatches associated with the non-data transfer access commands have zero latencies.

2. The method of claim 1, wherein the flag bit is set to a no-data-phase value.

3. The method of claim 1, wherein at least one of the non-data transfer access commands is a non-data transfer write command.

4. The method of claim 3, wherein the non-data transfer write command corresponds to a queue-able trim command that is associated with one logical sector that needs to be invalidated.

5. The method of claim 2, wherein at least a subset of the access commands are data transfer access commands, and wherein each data transfer access command comprises the flag bit that is set to a data-phase value.

6. The method of claim 5, wherein the non-data transfer access commands have the same opCode as the data transfer access commands.

7. The method of claim 3, wherein the dispatching further comprises:

dispatching the non-data transfer write command; and

receiving a complete status associated with the non-data transfer write command from the NVM with no delay.

8. The method of claim 3, wherein the non-data transfer write command is handled by the NVM at a later time.

9. The method of claim 3, wherein the non-data transfer write command is executed by the NVM concurrently with other commands.

10. The method of claim 1, wherein at least one of the non-data transfer access commands is a non-data transfer read command.

11. The method of claim 10, wherein the non-data transfer read command corresponds to an anticipatory fetch command with no data transfer.

12. A system comprising:

a non-volatile memory (“

NVM”

);

a bus;

a bus controller operative to communicate with the NVM over the bus; and

control circuitry operative to;

determine deterministic read patterns associated with a plurality of logical block addresses (“

LBAs”

) based on past read commands issued by an application;

receive a data request from the application, wherein the data request has a LBA range that is associated with a deterministic read pattern of the deterministic read patterns;

direct the bus controller to dispatch a data transfer read command associated with the LBA range to the NVM over the bus;

determine at least one additional LBA range based on the deterministic read pattern; and

direct the bus controller to dispatch at least one non-data transfer read command associated with the at least one additional LBA range to the NVM over the bus.

13. The system of claim 12, wherein the data transfer read command comprises a flag bit set to a data-phase value, and wherein the at least one non-data transfer read command comprises a flag bit set to a no-data-phase value.

14. The system of claim 12, wherein the bus is a Serial Advanced Technology Attachment (“

SATA”

) bus.

15. The system of claim 12, further comprising first volatile memory comprising a queue, wherein the control circuitry is further operative to:

store the data transfer read command in the queue; and

direct the bus controller to dispatch the data transfer read command from the queue to the NVM.

16. The system of claim 12, wherein the NVM is operative to:

receive the data transfer read command from the control circuitry over the bus;

fetch first data associated with the data transfer read command; and

transmit the first data associated with the data transfer read command to the control circuitry across the bus.

17. The system of claim 16, wherein the NVM is operative to:

receive the at least one non-data transfer read command from the control circuitry over the bus; and

pre-fetch second data associated with the at least one non-data transfer read command during a latency period associated with the transmission of the first data across the bus.

18. The system of claim 17, wherein the NVM comprises second volatile memory comprising a cache, and wherein the NVM is operative to store the second data in the cache of the NVM.

19. The system of claim 18, wherein the control circuitry is operative to:

receive a second data request from the application associated with the at least one additional LBA range; and

direct the bus controller to dispatch a second data transfer read command associated with the at least one additional LBA range to the NVM across the bus.

20. The system of claim 19, wherein the NVM is operative to:

receive the second data transfer read command from the control circuitry over the bus; and

transmit the second data stored in the cache to the control circuitry across the bus.

21. The system of claim 18, wherein the NVM is operative to:

determine that a second data transfer read command associated with the at least one additional LBA range has not been received over the bus after a pre-determined amount of time; and

remove the second data from the second volatile memory.

22. A memory interface for accessing a non-volatile memory (“

NVM”

), the memory interface comprising;

a bus controller operative to communicate with the NVM; and

control circuitry operative to;

track read behavior of an application over a period of time to determine non-random read patterns;

upon receiving a data request corresponding to a logical block address (“

LBA”

) range from the application, determine a plurality of LBA ranges that are highly associated with the LBA range based on the non-random read patterns; and

direct the bus controller to dispatch a set of non-data transfer read commands associated with the plurality of LBA ranges across a bus, thereby allowing the NVM to pre-fetch data associated with the plurality of LBA ranges without transmitting the data to the control circuitry.

23. The memory interface of claim 22, wherein the control circuitry is operative to dispatch the set of non-data transfer read commands in a non-sequential LBA order.

24. The memory interface of claim 22, wherein the control circuitry is operative to:

receive data requests corresponding to the plurality of LBA ranges;

dispatch data transfer read commands corresponding to the plurality of LBA ranges to the NVM over the bus; and

receive data associated with the data transfer read commands from the NVM with minimal latencies.