STORAGE DEVICE HAVING NONVOLATILE MEMORY DEVICE AND WRITE METHOD

• US 20130326119A1
• Filed: 03/06/2013
• Published: 12/05/2013
• Est. Priority Date: 06/01/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Dong-Hoon Ham, Intae Hwang, Jong-Nam Baek, Joonho Lee, Sang-Wook Yoo
• Inventors: BAEK, JONG-NAM, LEE, JOONHO, HAM, DONG-HOON, YOO, SANG-WOOK, HWANG, INTAE
• Granted Patent: US 9,715,444 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1471 involving logging of persistent data for recovery
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies

Abstract

Disclosed is a method of writing data in a storage device including a nonvolatile memory device. The method includes receiving write data with a write request, detecting a number of free blocks, if the detected number of free blocks is less than a threshold value, allocating a log block only in accordance with a sub-block unit, but if the detected number of free blocks is not less than the threshold value, allocating the log block in accordance with one of the sub-block unit and a physical block unit, wherein the sub-block unit is smaller than the physical block unit.

Claims

1. A method of storing write data in a storage device including a nonvolatile memory device having a memory cell array of nonvolatile memory cells, the method comprising:

receiving write data in conjunction with a write request indicating a write operation;

in response to the write request, detecting a number of free blocks available in the memory cell array;

if the detected number of free blocks is less than a threshold value, allocating a log block only in accordance with a sub-block unit, and if the detected number of free blocks is not less than the threshold value, allocating the log block in accordance with one of the sub-block unit and a physical block unit, wherein the sub-block unit is smaller than the physical block unit; and

executing the write operation for the write data according to the log block.

2. The method of claim 1, further comprising:

if the detected number of free blocks is not less than the threshold value, determining whether the write data has a random write pattern.

3. The method of claim 2, further comprising:

upon determining that the write data has a random pattern, allocating the log block in accordance with a sub-block unit, else allocating the log block in accordance with the physical block unit.

4. The method of claim 2, wherein determining whether the write data has a random write pattern comprises evaluating a set of addresses associated with the write data.

5. The method of claim 4, wherein evaluating the set of addresses associated with the write data comprises determining whether the set of addresses are in-place-order addresses.

6. The method of claim 4, wherein evaluating the set of addresses associated with the write data comprises determining whether the set of addresses are discontinuous.

7. The method of claim 1, wherein the memory cell array is a three-dimensional memory cell array.

8. The method of claim 1, wherein the nonvolatile memory cells are NAND flash memory cells, and

a physical block defining the physical block unit includes NAND flash memory cells arranged in strings commonly connected to at least one word line.

9. The method of claim 8, wherein the physical block may be erased during one erase operation performed by the nonvolatile memory device.

10. The method of claim 8, wherein the physical block includes multiple sub-blocks each being defined by the sub-block unit, and

each sub-block includes NAND flash memory cells commonly connected to at least a portion of only one word line.

11. The method of claim 10, wherein each one of the sub-blocks may be independently erased during one erase operation performed by the nonvolatile memory device.

12. A method of storing write data in a storage device including a nonvolatile memory device having a memory cell array of nonvolatile memory cells, the method comprising:

receiving write data in conjunction with a write request indicating a write operation;

in response to the write request, determining a number of bad blocks among a plurality of memory blocks in the memory cell array;

if the number of bad blocks is greater than a threshold value, allocating a log block only in accordance with a sub-block unit, and if the number of bad blocks is not greater than the threshold value, allocating the log block in accordance with one of the sub-block unit and a physical block unit, wherein the sub-block unit is smaller than the physical block unit; and

executing the write operation for the write data according to the log block.

13. The method of claim 12, further comprising:

if the number of bad blocks is not greater than the threshold value, determining whether the write data has a random write pattern.

14. The method of claim 13, further comprising:

upon determining that the write data has a random pattern, allocating the log block in accordance with a sub-block unit, else allocating the log block in accordance with the physical block unit.

15. The method of claim 13, wherein determining whether the write data has a random write pattern comprises evaluating a set of addresses associated with the write data.

16. The method of claim 15, wherein evaluating the set of addresses associated with the write data comprises determining whether the set of addresses are in-place-order addresses.

17. The method of claim 15, wherein evaluating the set of addresses associated with the write data comprises determining whether the set of addresses are discontinuous.

18. The method of claim 12, wherein the memory cell array is a three-dimensional memory cell array.

19. The method of claim 12, wherein the nonvolatile memory cells are NAND flash memory cells, and

a physical block defining the physical block unit includes NAND flash memory cells arranged in strings commonly connected to at least one word line.

20. The method of claim 19, wherein the physical block may be erased during one erase operation performed by the nonvolatile memory device.

21. The method of claim 19, wherein the physical block includes multiple sub-blocks each being defined by the sub-block unit, and

each sub-block includes NAND flash memory cells commonly connected to at least a portion of only one word line.

22. The method of claim 21, wherein each one of the sub-blocks may be independently erased during one erase operation performed by the nonvolatile memory device.