BROADCAST OPERATION ON MASK REGISTER

• US 20130326192A1
• Filed: 12/22/2011
• Published: 12/05/2013
• Est. Priority Date: 12/22/2011
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ould-Ahmed-Vall, Elmoustapha, Girkar, Milind Baburao, Corbal San Adrian, Jesus, Valentine, Robert C., Sair, Suleyman
• Application Number:
  US13/995,430
• Publication Number:
  US 20130326192A1
• Time in Patent Office: Days
• US Class Current: 712/205
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30038 using a mask
• CPC Class Codes: G06F 9/30098 Register arrangements

Abstract

Embodiments of systems, apparatuses, and methods for performing a mask broadcast instruction in a computer processor are described. In some embodiments, the execution of a mask broadcast instruction causes a broadcast of a data element of the source operand to a destination register of the destination operand according to the broadcast size.

Claims

1. A method of performing mask broadcast instruction in a computer processor, comprising:

fetching the mask broadcast instruction, wherein the mask broadcast instruction includes a destination operand, a source operand, and broadcast size;

decoding the fetched mask broadcast instruction; and

executing the decoded mask broadcast instruction to perform a broadcast of a data element of the source operand to a destination register of the destination operand according to the broadcast size.

2. The method of claim 1, wherein the destination register is a mask register.

3. The method of claim 1, wherein the data element is a least significant bit of data in the source operand.

4. The method of claim 1, wherein the broadcast size is derived from the name of the mask register instruction.

5. The method of claim 4, wherein the broadcast size is selected from the group consisting of 8, 16, 32, and 64 bits.

6. The method of claim 1, wherein the source is a 512-bit register.

7. The method of claim 1, wherein the broadcasting is done in parallel.

8. The method of claim 1, wherein the to perform a broadcast further comprises to combine the data element of the source with another data element of another source into a result, and to broadcast the result to the destination register.

9. A non-transitory machine-readable medium having executable instructions to cause one or more processing units to perform a method to protect data stored in a storage system of a device from malware alternation, the method, comprising:

in response to a mask broadcast instruction that includes a destination operand, a first source operand, and broadcast size,

retrieving a data element of the first source operand as a broadcast data,

for each destination position of the destination operand according to the broadcast size, storing that broadcast data into the destination position.

10. The non-transitory machine-readable medium of claim 9, further comprising for the each destination position:

combining the broadcast data with another data element of a second source operand.

11. The non-transitory machine-readable medium of claim 10, wherein the combining in an AND operation.

12. The non-transitory machine-readable medium of claim 10, wherein the second operand is a 512-bit register.

13. The non-transitory machine-readable medium of claim 10, wherein the combining is done in parallel.

14. The non-transitory machine-readable medium of claim 9, wherein the destination operand is a 16-bit mask register.

15. The non-transitory machine-readable medium of claim 9, wherein the data element is a least significant bit of data in the source operand.

16. The non-transitory machine-readable medium of claim 9, wherein the broadcast size is derived from the name of the mask register instruction.

17. The non-transitory machine-readable medium of claim 16, wherein the broadcast size is selected from the group consisting of 8, 16, 32, and 64 bits.

18. The non-transitory machine-readable medium of claim 9, wherein the second source operand is a 512-bit register.

19. A processor comprising;

a hardware decoder to decode a mask broadcast instruction, wherein the mask broadcast instruction includes a writemask operand, a destination operand, a first source operand, and a second source operand;

execution logic to perform a broadcast of a data element of the source operand to a destination register of the destination operand according to the broadcast size.

20. The processor of claim 19, further comprising:

a source register to store the first data element; and

a destination register to store the broadcasted data element.