SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF

• US 20130326267A1
• Filed: 06/03/2013
• Published: 12/05/2013
• Est. Priority Date: 06/04/2012
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: MOON, Young-Suk, LEE, Hyung-Dong, KWON, Yong-Kee, KIM, Hong-Sik, YANG, Hyung-Gyun, KIM, Joon-Woo
• Granted Patent: US 9,304,854 B2
• Time in Patent Office: Days
• US Class Current: 714/6.3
• CPC Class Codes: G06F 11/1024 Identification of the type of error
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/141 for bus or memory accesses
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/2094 Redundant storage or storage space G06F11/2056 takes precedence
• CPC Class Codes: G11C 2029/0411 Online error correction

Abstract

A semiconductor device includes a controller configured to receive a request for a first memory device, determine whether or not a multi-bit error has occurred at a requested address of the first memory device, and process the request on a second memory device instead of the first memory device, when the multi-bit error has occurred.

Claims

1. A semiconductor device comprising:

a controller configured to receive a request for a first memory device, determine whether or not a multi-bit error has occurred at a requested address of the first memory device, and process the request on a second memory device instead of the first memory device, when the multi-bit error has occurred.

2. The semiconductor device of claim 1, wherein the controller processes the request for the first memory device when a single-bit error has occurred at the requested address of the first memory device, and registers multi-bit error occurrence information corresponding to the request address when a multi-bit error exists in data outputted from the first memory device.

3. The semiconductor device of claim 2, wherein the controller controls the second memory device to perform the request for the first memory device on the second memory device, when the single-bit error has occurred.

4. The semiconductor device of claim 3, wherein the request comprises any one of a write request and a read request.

5. The semiconductor device of claim 2, wherein when a single-bit error exists in data outputted from the first memory device as a result obtained by processing the request for the first memory device, the controller controls the second memory device to update single-bit error occurrence information corresponding to the requested address in the second memory device.

6. The semiconductor device of claim 5, wherein the controller controls an ECC block to correct the single-bit error contained in the data from the first memory device.

7. The semiconductor device of claim 1, wherein the controller controls the first memory device to process the request when none of a single-bit error and the multi-bit error has occurred at the requested address of the first memory device, and registers single-bit error occurrence information corresponding to the requested address when a single-bit error exists in data outputted from the first memory device as a processing result.

8. The semiconductor device of claim 7, wherein when a multi-bit error exists in the data from the first memory device, the controller reports the error.

9. The semiconductor device of claim 2, wherein the multi-bit error occurrence information is stored in the second memory device.

10. The semiconductor device of claim 2, wherein the single-bit error occurrence information is stored in the second memory device.

11. The semiconductor device of claim 10, wherein the controller removes soft error information in the single-bit error occurrence information stored in the second memory device.

12. The semiconductor device of claim 11, wherein the controller removes the soft error information at each predetermined period.

13. The semiconductor device of claim 11, wherein the controller primarily selects addresses at which a single-bit error occurred K or less times (K is a natural number) in the second memory device, controls the first memory device to perform L read requests (L is a natural number) at the primarily-selected addresses, secondarily selects addresses at which a single-bit error occurred M or less times (M is a natural number less than K+L) in the second memory device, and controls the second memory device to delete the secondarily-selected addresses and single-bit error occurrence information corresponding to the secondarily-selected addresses, in order to remove the soft error information.

14. The semiconductor device of claim 1, further comprising the second memory device.

15. The semiconductor device of claim 6, further comprising the ECC block.

16. The semiconductor device of claim 1, wherein further comprising:

a command generator configured to generate a control command for controlling the first memory device in response to the request; and

a control selector configured to provide any one of the control command generated by the command generator and a control command generated by the controller to process the request for the first memory device, to the first memory device according to selection of the controller.

17. The semiconductor device of claim 16, further comprising an arbitration block configured to determine the processing sequence of a plurality of requests,

wherein the controller temporarily stops the operation of the arbitration block when the controller is intended to directly control the first memory device.

18. A system comprising a control device configured to control a semiconductor memory device,

wherein the control device comprises:

a memory device configured to store an address at which a multi-bit error has occurred in the semiconductor memory device and data corresponding to the address; and

a controller configured to receive a request for the semiconductor memory device, determine whether or not a multi-bit error has occurred at a requested error of the semiconductor memory device, and process the request on the memory device instead of the semiconductor memory device when a multi-bit error has occurred.

19. The system of claim 18, wherein the memory device further stores an address at which a single-bit error has occurred in the semiconductor memory device and data corresponding to the address, and

the controller controls the memory device to check whether or not a single-bit error has occurred at the requested address during the request for the semiconductor memory device, processes the request for the semiconductor memory device when a single-bit error has occurred at the requested address, and stores multi-bit error occurrence information corresponding to the requested address in the memory device when a multi-bit error occurred in data outputted from the semiconductor memory device as a result obtained by processing the request for the semiconductor memory device.

20. The system of claim 19, wherein the control device processes the request for the semiconductor memory device on the memory device when a single-bit error has occurred at the requested error.

21. The system of claim 20, wherein the request comprises any one of a read request and a write request.

22. The system of claim 19, wherein the controller controls the memory device to update single-bit error occurrence information corresponding to the requested address when a single-bit error occurred in data outputted from the semiconductor memory device as a result obtained by processing the request for the semiconductor memory device.

23. The system of claim 20, wherein the controller further comprises an ECC block configured to correct the single-bit error contained in the data outputted from the semiconductor memory device.

24. The system of claim 18, wherein the controller controls the semiconductor memory device to process the request when none of a single-bit error and the multi-bit error has occurred at the requested address of the semiconductor memory device, and controls the memory device to register single-bit error occurrence information corresponding to the requested address in the memory device when a single-bit error exists in the data from the semiconductor memory device as the processing result.

25. The system of claim 19, wherein the controller removes soft error information in the single-bit error occurrence information stored in the memory device.

26. The system of claim 25, wherein the controller removes the soft error information at each predetermined period.

27. The system of claim 25, wherein the controller primarily selects addresses at which a single-bit error occurred K or less times (K is a natural number) in the memory device, controls the semiconductor memory device to perform L read requests (L is a natural number) at the primarily-selected addresses, secondarily selects addresses at which a single-bit error occurred M or less times (M is a natural number less than K+L) in the memory device, and controls the memory device to delete the secondarily-selected addresses and single-bit error occurrence information corresponding to the secondarily-selected addresses, in order to remove the soft error information.

28. The system of claim 18, wherein the controller comprises:

a command generator configured to generate a control command for controlling the semiconductor memory device in response to the request; and

a control selector configured to provides any one of the control command from the command generator and a control command generated by the controller to process the request for the memory device to the memory device according to selection of the controller.

29. The system of claim 18, wherein the controller further comprises an arbitration block configured to determine the processing sequence of a plurality of requests, and the controller temporarily stops the operation of the arbitration block when the controller is intended to directly control the semiconductor memory device.