THIN-FILM TRANSISTOR ELEMENT AND METHOD FOR MANUFACTURING SAME, ORGANIC ELECTROLUMINESCENT DISPLAY ELEMENT, AND ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE

• US 20130328035A1
• Filed: 08/16/2013
• Published: 12/12/2013
• Est. Priority Date: 11/14/2011
• Status: Active Grant

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: OKUMOTO, Yuko, MIYAMOTO, Akihito, UKEDA, Takaaki
• Granted Patent: US 8,941,115 B2
• Time in Patent Office: Days
• US Class Current: 257/40
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H10K 10/466 Lateral bottom-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/484 characterised by the channel regions
• CPC Class Codes: H10K 50/844 Encapsulations
• CPC Class Codes: H10K 59/873 Encapsulations
• CPC Class Codes: H10K 71/00 Manufacture or treatment specially adapted for the organic devices covered by this subclass
• CPC Class Codes: H10K 71/13 using printing techniques, e.g. ink-jet printing or screen printing

Abstract

A thin film transistor element includes a gate electrode, an insulating layer formed on the gate electrode, and partition walls formed on the insulating layer and defining a first aperture above the gate electrode. The thin film transistor element further includes, at a bottom portion of the first aperture, a source electrode and a drain electrode that are in alignment with each other with a gap therebetween, a liquid-philic layer, and a semiconductor layer that covers the source electrode, the drain electrode, and the liquid-philic layer as well as gaps therebetween. The liquid-philic layer has higher liquid philicity than the insulating layer, and in plan view of the bottom portion of the first aperture, a center of area of the liquid-philic layer is offset from a center of area of the bottom portion of the first aperture.

Claims

1. A thin film transistor element comprising:

a gate electrode;

an insulating layer disposed on the gate electrode;

a source electrode and a drain electrode disposed on the insulating layer with a gap therebetween;

a semiconductor layer disposed on the source electrode and the drain electrode so as to cover the source electrode and the drain electrode and fill the gap between the source electrode and the drain electrode, and being in contact with the source electrode and the drain electrode;

a liquid-philic layer disposed on the insulating layer and having higher liquid philicity than the insulating layer, the liquid-philic layer being separate from the source electrode and the drain electrode, and

partition walls disposed on the insulating layer and having liquid-repellant surfaces, the partition walls defining at least a first aperture and a second aperture, wherein

the first aperture surrounds at least a part of each of the source electrode, the drain electrode, and the liquid-philic layer, a bottom portion of the first aperture thus including a source electrode portion being a bottom portion of the source electrode, a drain electrode portion being a bottom portion of the drain electrode, and a liquid-philic layer portion being a bottom portion of the liquid-philic layer,

the second aperture is located apart from the first aperture with a gap therebetween and the semiconductor layer is not formed within an area surrounded by the second aperture, and

in plan view of the bottom portion of the first aperture, a center of area of the liquid-philic layer portion is offset from a center of area of the bottom portion of the first aperture in a first direction opposite a direction of the second aperture.

2. The thin film transistor element of claim 1, wherein

the bottom portion of the first aperture includes a first portion where the source electrode portion, the drain electrode portion, and the liquid-philic layer portion do not exist and thus, where the insulating layer is in direct contact with the semiconductor layer, the first portion being within an area of the bottom portion of the first aperture located in the direction of the second aperture.

3. The thin film transistor element of claim 2, wherein

the bottom portion of the first aperture includes a second portion where the source electrode portion, the drain electrode portion, and the liquid-philic layer portion do not exist and thus, where the insulating layer is in direct contact with the semiconductor layer, the second portion being within an area of the bottom portion of the first aperture located in the first direction, and

in plan view of the bottom portion of the first aperture, an area of the first portion is greater than an area of the second portion.

4. The thin film transistor element of claim 1, wherein

the liquid-philic layer is formed by using a same material as used for forming the source electrode and the drain electrode, and

the liquid-philic layer is located apart from each of the source electrode and the drain electrode.

5. The thin film transistor element of claim 1, wherein

in plan view of the bottom portion of the first aperture,

a center of a total of areas of the source electrode portion and the drain electrode portion coincides with the center of area of the bottom portion of the first aperture.

6. The thin film transistor element of claim 1, wherein

in plan view of the bottom portion of the first aperture,

a center of a total of areas of the source electrode portion, the drain electrode portion, and the liquid-philic layer portion is offset from the center of area of the bottom portion of the first aperture in the first direction.

7. The thin film transistor element of claim 1, wherein

at the bottom portion of the first aperture,

a side, in the first direction, of the liquid-philic layer portion is in contact with a side surface portion of the partition walls facing the first aperture.

8. The thin film transistor element of claim 1, wherein

a liquid repellency of the surfaces of the partition walls is greater than a liquid repellency of a surface of the insulating layer that is in contact with the semiconductor layer, and

the liquid repellency of the surface of the insulating layer that is in contact with the semiconductor layer is greater than a liquid repellency of a surface of each of the source electrode, the drain electrode, and the liquid-philic layer.

9. The thin film transistor element of claim 1, wherein

the semiconductor layer is formed within an area surrounded by the first aperture, and thus, the area surrounded by the first aperture functions as a channel portion, and

the area surrounded by the second aperture does not function as a channel portion.

10. The thin film transistor element of claim 9, wherein

one of the source electrode and the drain electrode extends into a bottom portion of the second aperture, or the bottom portion of the second aperture includes a wire formed for electrically connecting with one of the source electrode and the drain electrode.

11. An organic EL display element comprising:

the thin film transistor element of claim 1;

a planarizing film formed above the thin film transistor element and having a contact hole formed therein;

a lower electrode formed so as to cover the planarizing film and a side surface of the planarizing film defining the contact hole, and electrically connected with one of the source electrode and the drain electrode;

an upper electrode formed above the lower electrode; and

an organic light-emitting layer interposed between the lower electrode and the upper electrode.

12. An organic EL display element comprising:

the thin film transistor element of claim 9;

a planarizing film formed above the thin film transistor element and having a contact hole formed therein;

a lower electrode formed so as to cover the planarizing film and a side surface of the planarizing film defining the contact hole, and electrically connected with one of the source electrode and the drain electrode;

an upper electrode formed above the lower electrode; and

an organic light-emitting layer interposed between the lower electrode and the upper electrode, wherein

the contact hole is in communication with the second aperture of the thin film transistor element.

13. An organic EL display device comprising the organic EL display element of claim 11.

14. A method of manufacturing a thin film transistor element comprising:

forming a gate electrode on a substrate;

forming an insulating layer on the gate electrode;

forming a source electrode and a drain electrode, and a liquid-philic layer on the insulating layer, wherein the source electrode and the drain electrode are formed with a gap therebetween, and the liquid-philic layer is formed so as to be located apart from the source electrode and the drain electrode, the liquid-philic layer having higher liquid philicity than the insulating layer;

depositing a layer of photosensitive resist material such that, above the insulating layer, the layer of photosensitive resist material covers the source electrode and the drain electrode;

forming partition walls on the insulating layer by performing mask exposure and patterning of the layer of photosensitive resist material, the partition walls having liquid-repellant surfaces and defining at least a first aperture and a second aperture; and

forming a semiconductor layer by applying semiconductor material with respect to the first aperture and drying the semiconductor material so applied, wherein the semiconductor layer is formed so as to be in contact with the source electrode and the drain electrode, wherein

the first aperture surrounds at least a part of each of the source electrode, the drain electrode, and the liquid-philic layer, a bottom portion of the first aperture thus including a source electrode portion being a bottom portion of the source electrode, a drain electrode portion being a bottom portion of the drain electrode, and a liquid-philic layer portion being a bottom portion of the liquid-philic layer,

the second aperture is located apart from the first aperture with a gap therebetween and the semiconductor layer is not formed within an area surrounded by the second aperture, and

the partition walls are formed such that

in plan view of the bottom portion of the first aperture, a center of area of the liquid-philic layer portion is offset from a center of area of the bottom portion of the first aperture in a first direction opposite a direction of the second aperture.

15. The method of claim 14, wherein

the forming, on the insulating layer, of the source electrode, the drain electrode, and the liquid-philic layer includes sub-steps of:

forming a metal layer on the insulating layer; and

etching the metal layer so formed.

16. The method of claim 14, wherein

the partition walls are formed such that the bottom portion of the first aperture includes a first portion where the source electrode portion, the drain electrode portion, and the liquid-philic layer portion do not exist and thus, where the insulating layer is to come in direct contact with the semiconductor layer, the first portion being within an area of the bottom portion of the first aperture located in the direction of the second aperture.

17. The method of claim 16, wherein

the partition walls are formed such that

the bottom portion of the first aperture includes a second portion where the source electrode portion, the drain electrode portion, and the liquid-philic layer portion do not exist and thus, where the insulating layer is to come in direct contact with the semiconductor layer, the second portion being within an area of the bottom portion of the first aperture located in the first direction, and

in plan view of the bottom portion of the first aperture, an area of the first portion is greater than an area of the second portion.

18. The method of claim 14, wherein

the forming of the insulating layer, the forming of the source electrode, the drain electrodes, and the liquid-philic layer, the forming of the partition walls, and the forming of the semiconductor layer are performed such that

a liquid repellency of the surfaces of the partition walls is greater than a liquid repellency of a surface of the insulating layer that is to come in contact with the semiconductor layer, and

the liquid repellency of the surface of the insulating layer is greater than a liquid repellency of a surface of each of the source electrode, the drain electrode, and the liquid-philic layer.