SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

• US 20130328062A1
• Filed: 06/07/2013
• Published: 12/12/2013
• Est. Priority Date: 06/07/2012
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Hisamoto, Digh, Tega, Naoki, Konishi, Kumiko, Matsushima, Hiroyuki
• Granted Patent: US 9,054,174 B2
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: H01L 21/0495 Schottky electrodes
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/782 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

In a MOSFET using a SiC substrate, a source region having low resistance and high injection efficiency is formed without performing a high-temperature heat treatment.

A vertical Schottky barrier transistor in which a source region SR on a SiC epitaxial substrate is constituted by a metal material is formed. The source region SR composed of a metal material can be brought into a low resistance state without performing a high-temperature activation treatment. Further, by segregating a conductive impurity DP at an interface between the source region SR composed of a metal material and the SiC epitaxial substrate, the Schottky barrier height can be reduced, and the carrier injection efficiency from the source region SR can be improved.

Claims

1. A semiconductor device, comprising a field-effect transistor formed in a first region of a semiconductor substrate, wherein the field-effect transistor includes:

(a) the semiconductor substrate of a first conductivity type which serves as a drain region;

(b) a drift layer of the first conductivity type which is formed on the semiconductor substrate and has a lower impurity concentration than the semiconductor substrate;

(c) a well region of a second conductivity type which is in contact with the drift layer;

(d) a source region which is in contact with the well region and is constituted by a metal material;

(e) a channel forming region which is sandwiched by the source region and the drift layer in the well region;

(f) a gate insulating film which is contact with the channel forming region; and

(g) a gate electrode which is in contact with the gate insulating film.

2. The semiconductor device according to claim 1, wherein

the semiconductor substrate and the drift layer are formed from silicon carbide doped with an impurity of the first conductivity type, and

the well region is formed from silicon carbide doped with an impurity of the second conductivity type.

3. The semiconductor device according to claim 1, wherein a conductive impurity is segregated at an interface between the source region and the well region.

4. The semiconductor device according to claim 3, wherein the conductive impurity is phosphorus or arsenic.

5. The semiconductor device according to claim 1, wherein the metal material is nickel silicide.

6. The semiconductor device according to claim 1, wherein the semiconductor device has a diode in a second region of the semiconductor substrate.

7. The semiconductor device according to claim 6, wherein the second region is formed to surround the periphery of the first region.

8. The semiconductor device according to claim 1, wherein the contact between the source region and the well region is Schottky contact.

9. A method for producing a semiconductor device, comprising the steps of:

(a) preparing a semiconductor substrate composed of silicon carbide doped with an impurity of a first conductivity type;

(b) forming a drift layer, which is composed of silicon carbide doped with an impurity of the first conductivity type and has a lower impurity concentration than the semiconductor substrate, on the semiconductor substrate;

(c) forming a well region which is in contact with the drift layer and is composed of silicon carbide doped with an impurity of a second conductivity type;

(d) forming a source region which is in contact with the well region and is composed of a metal material;

(e) forming a gate insulating film which is contact with a channel forming region in which a channel is formed in the well region; and

(f) forming a gate electrode which is in contact with the gate insulating film.

10. The method for producing a semiconductor device according to claim 9, wherein the step (d) includes the steps of:

(d1) forming a polysilicon film which is in contact with the well region;

(d2) forming a metal film on the polysilicon film; and

(d3) subjecting the semiconductor substrate to a heat treatment after the step (d2) to react the polysilicon film with the metal film, thereby forming the source region composed of a metal silicide film.

11. The method for producing a semiconductor device according to claim 9, wherein the step (d) includes the steps of:

(d1) forming a polysilicon film which is in contact with the well region;

(d2) doping a conductive impurity into the polysilicon film;

(d3) forming a metal film on the polysilicon film after the step (d2); and

(d4) subjecting the semiconductor substrate to a heat treatment after the step (d3) to react the polysilicon film with the metal film, thereby forming the source region composed of a metal silicide film, and segregating the conductive impurity at an interface between the source region and the well region.