INDUCTOR DEVICE AND FABRICATION METHOD

• US 20130328164A1
• Filed: 11/30/2012
• Published: 12/12/2013
• Est. Priority Date: 06/06/2012
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Ling Liu
• Inventors: CHENG, JENHAO, WANG, XINING, LIU, LING
• Granted Patent: US 8,884,399 B2
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Various embodiments provide inductor devices and fabrication methods. An exemplary inductor device can include a plurality of planar spiral wirings isolated by a dielectric layer. The planar spiral wirings can be connected by conductive pads formed over the dielectric layer and by conductive plugs formed in the dielectric layer. In one embodiment, a third planar spiral wiring can be formed over a second planar spiral wirings that is formed over a first planar spiral wiring. The third planar spiral wiring can be configured in parallel with the first third planar spiral wiring. The second planar spiral wiring can be configured in series with the first and third planar spiral wirings configured in parallel.

Claims

1. An inductor device comprising:

a semiconductor substrate;

a first planar spiral wiring disposed over the semiconductor substrate;

a second planar spiral wiring disposed over the first planar spiral wiring; and

a third planar spiral wiring disposed over the second planar spiral wiring,

wherein each of the first, the second, and the third planar spiral wirings includes an outer spiral metal wiring and an inner spiral metal wiring including at least two isolated sub-metal-lines each connecting to the outer spiral metal wiring, and

wherein one sub-metal-line of the at least two isolated sub-metal-lines in each of the first, the second, and the third planar spiral wirings is connected to one another, and the outer spiral metal wiring in the first planar spiral wiring is connected to the outer spiral metal wiring in the third planar spiral wiring such that the first and the third planar spiral wirings are configured in parallel and the second planar spiral wiring is configured in series with the first and the third planar spiral wirings configured in parallel.

2. The device of claim 1, further including:

a first dielectric layer disposed between the semiconductor substrate and the first planar spiral wiring;

a second dielectric layer disposed between the first planar spiral wiring and the second planar spiral wiring; and

a third dielectric layer disposed between the second planar spiral wiring and the third planar spiral wiring.

3. The device of claim 1, further including:

a first conductive plug connecting the one sub-metal-line of the at least two first sub-metal-lines in the first planar spiral wiring to the one sub-metal-line of the at least two sub-metal-lines in the second planar spiral wiring; and

a second conductive plug connecting the one sub-metal-line of the at least two first sub-metal-lines in the second planar spiral wiring to the one sub-metal-line of the at least two sub-metal-lines in the third planar spiral wiring.

4. The device of claim 1, wherein the inner spiral metal wiring in the first, the second, or the third planar spiral wiring includes about 2 to about 10 isolated sub-metal-lines.

5. The device of claim 1, wherein the outer spiral metal wiring in the first, the second, or the third planar spiral wiring includes about 1 to about 10 isolated sub-metal-lines.

6. The device of claim 1, wherein a distance between adjacent sub-metal-lines in each of the first, the second, and the third planar spiral wirings is about 0.001 μ

m to about 100 μ

m.

7. The device of claim 1, wherein each sub-metal-line in the first, the second, and the third planar spiral wirings has a width of about 0.1 μ

m to about 100 μ

m.

8. The device of claim 1, wherein the first, the second, or the third planar spiral wiring is made of a material including copper or aluminum, and has a shape selected from a quadrilateral, hexagonal, octagonal or circular shape.

9. The device of claim 1, wherein the first, the second, or the third planar spiral wiring has a thickness of about 0.1 μ

m to about 100 μ

m, and an inner radius of about 5 μ

m to about 1 m.

10. The device of claim 1, wherein the outer spiral metal wiring in the first, the second, or the third planar spiral wiring is made by a single wire of copper and has a thickness of about 0.1 μ

m to about 100 μ

m.

11. A method for forming an inductor device comprising:

providing a semiconductor substrate;

forming a first planar spiral wiring over the semiconductor substrate.

forming a second planar spiral wiring over the first planar spiral wiring;

forming a third planar spiral wiring over the second planar spiral wiring, wherein each of the first, the second, and the third planar spiral wirings includes an outer spiral metal wiring and an inner spiral metal wiring including at least two isolated sub-metal-lines each connecting to the outer spiral metal wiring;

connecting one sub-metal-line of the at least two isolated sub-metal-lines in each of the first, the second, and the third planar spiral wirings to one another; and

connecting the outer spiral metal wiring in the first planar spiral wiring to the outer spiral metal wiring in the third planar spiral wiring such that the first and the third planar spiral wirings are configured in parallel and the second planar spiral wiring is configured in series with the first and the third planar spiral wirings configured in parallel.

12. The method of claim 11, further including:

forming a first dielectric layer over the semiconductor substrate, prior to forming the first planar spiral wiring;

forming a second dielectric layer over the first planar spiral wiring, prior to forming the second planar spiral wiring; and

forming a third dielectric layer over the second planar spiral wiring, prior to forming the third planar spiral wiring.

13. The method of claim 11, wherein the connecting of the one sub-metal-line in each of the first, the second, and the third planar spiral wirings includes:

forming a first conductive plug in a second dielectric layer to connect the one sub-metal-line in the first planar spiral wiring to the one sub-metal-line in the second planar spiral wiring; and

forming a second conductive plug in a third dielectric layer to connect the one sub-metal-line in the second planar spiral wiring to the one sub-metal-line in the third planar spiral wiring.

14. The method of claim 11, wherein the connecting of the outer spiral metal wirings in the first and the third planar spiral wirings includes:

forming a first contact pad connecting to the outer spiral metal wirings in the first planar spiral wiring;

forming a third contact pad connecting to the outer spiral metal wirings in the third planar spiral wiring; and

forming a third conductive plug connecting the first contact pad to the third contact pad.

15. The method of claim 11, wherein the inner spiral metal wiring in the first, the second, or the third planar spiral wiring includes about 2 to about 10 isolated sub-metal-lines, and the outer spiral metal wiring in the first, the second, or the third planar spiral wiring includes about 1 to about 10 isolated sub-metal-lines.

16. The method of claim 11, wherein a distance between adjacent sub-metal-lines in each of the first, the second, and the third planar spiral wirings is about 0.001 μ

m to about 100 μ

m.

17. The method of claim 11, wherein each sub-metal-line in the first, the second, and the third planar spiral wirings has a width of about 0.1 μ

m to about 100 μ

m.

18. The method of claim 11, wherein the first, the second, or the third planar spiral wiring is made of a material including copper or aluminum, and has a shape selected from a quadrilateral, hexagonal, octagonal or circular shape.

19. The method of claim 11, wherein the first, the second, or the third planar spiral wiring has a thickness of about 0.1 μ

m to about 100 μ

m, and an inner radius of about 5 μ

m to about 1 m.

20. The method of claim 11, wherein the outer spiral metal wiring in the first, the second, or the third planar spiral wiring is made by a single wire of copper and has a thickness of about 0.1 μ

m to about 100 μ

m.